Method for making dynamic random access memory cells having double-crown stacked capacitors with center posts

A method for fabricating a dynamic random access memory (DRAM) device having stacked capacitors comprising the steps of:

• forming field oxide areas on a semiconductor substrate while leaving device areas for fabrication of semiconductor devices;
• forming a gate oxide on said device areas;
• depositing and patterning an electrically conductive layer having a cap oxide to form gate electrodes over said device areas and word lines over said field oxide areas;
• forming lightly doped source/drain regions in said device areas adjacent to said gate electrodes;
• depositing and etching back a spacer silicon oxide layer to form spacers on sidewalls of said gate electrodes;
• forming source/drain contact regions in said device areas adjacent to said spacers thereby forming field effect transistors (FETs);
• depositing a first insulating layer over said device areas and said field oxide areas;
• depositing a second insulating layer on said first insulating layer;
• planarizing said second insulating layer;
• forming contact openings in said first and second insulating layers to said device areas where electrical contacts are desired for said stacked capacitors;
• and forming said stacked capacitors by,
• depositing a first polysilicon layer over said device areas and said field oxide areas, said first polysilicon layer filling said contact openings and making contact to said device areas;
• depositing a disposable third insulating layer on said first polysilicon layer;
• patterning by anisotropic plasma etching said third insulating layer to said first polysilicon layer leaving portions of said third insulating layer having vertical sidewalls over said contact openings;
• depositing a second polysilicon layer;
• anisotropically etching back said second polysilicon layer and forming first polysilicon spacers on said sidewalls of said third insulating layer;
• removing selectively said portions of said third insulating layer leaving said first polysilicon spacers on said first polysilicon layer;
• depositing a disposable fourth insulating layer over said first polysilicon spacers and on said first polysilicon layer;
• anisotropically plasma etching back said fourth insulating layer to form inner and outer insulating sidewall spacers on said first polysilicon spacers;
• depositing a third polysilicon layer on said inner and outer insulating sidewall spacers and on said first polysilicon layer;
• anisotropically plasma etching back said third polysilicon layer and said first polysilicon layer, thereby forming second polysilicon spacers on said outer insulating sidewall spacers while retaining said third polysilicon layer between said inner insulating sidewall spacers to form a center post, and further, said etching of said first polysilicon layer electrically isolating from each other bottom electrodes for said stacked capacitors;
• removing selectively said inner and outer insulating sidewall spacers to form said bottom electrodes having said center post;
• forming a capacitor dielectric layer on said bottom electrodes;
• depositing and patterning a fourth polysilicon layer to form top electrodes thereby completing said DRAM device with said stacked capacitors.