Jtag testing of buses using plug-in cards with Jtag logic mounted thereon

A JTAG plug-in test card for use in testing a plurality of bus connections on a motherboard which interface with unpopulated plug-in peripheral or expansion slots, said test card comprising:

• a first connector portion which engages with said unpopulated plug-in peripheral or expansion slots to provide electrical communication to said bus connections;
• a second connector portion for inputting JTAG control and data signals;
• a third connector portion coupled to at least one of said JTAG control signals and providing said at least one JTAG control signal for output;
• buffer circuitry coupled to at least a portion of said JTAG control and data signals, including:
• a boundary scan register;
• a TAP controller;
• and
• an instruction register;
• an input bus which provides an input path by which signals from said connector are provided as inputs to said boundary scan register;
• an output bus by which output signals from said boundary scan register are provided to said connector and thereby to said plurality of bus connections, and wherein said buffer circuitry is used solely as a JTAG test device and not as a buffer.

A JTAG plug-in test card for use in testing a plurality of bus connections on a motherboard which interface with a plug-in bus slot, said test card comprising:

• a first connector portion which engages with said plug-in bus slot;
• a second connector portion which provides an interface to JTAG data input and output lines and at which receives JTAG control lines;
• a third connector portion which is coupled to at least one of said JTAG control lines to thereby provide said at least one JTAG control line as an output;
• and
• an integrated circuit having a plurality of bus transceivers in electrical communication with said first connector portion to transmit data to and to receive data from said bus slot, said integrated circuit further including a JTAG interface which receives serial data and control signals from said second connector portion and which transfers data between said JTAG data lines and said bus transceivers thereby enabling said integrated circuit to operate as a JTAG test circuit which tests said bus slot and said plurality of bus connections, said integrated circuit not operating in accordance with the primary function of said integrated circuit, but as a JTAG test device.