US 5,852,570 AGranted

Semiconductor memory using select transistors coupled to sub-bitlines from different blocks

AssigneeSharp Kabushiki Kaisha

InventorsYasuhiro Hotta, Takeshi Nojima, Koji Komatsu

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Abstract

The semiconductor memory device of the invention includes: a semiconductor substrate; a first block; a second block adjacent to the first block; a main bitline; a first auxiliary conductive region; a first select transistor; and a first select line. The first block includes a first memory transistor having a first electrode, a second electrode and a gate electrode; a first sub-bitline including a part functioning as the first electrode of the first memory transistor; a second sub-bitline including a part functioning as the second electrode of the first memory transistor; and a first word line including a part functioning as the gate electrode of the first memory transistor, while the second block includes: a second memory transistor having a third electrode, a fourth electrode and a gate electrode; a third sub-bitline including a part functioning as the third electrode of the second memory transistor; a fourth sub-bitline including a part functioning as the fourth electrode of the second memory transistor; and a second word line including a part functioning as the gate electrode of the second memory transistor.

Claims22

Dependent claims

A semiconductor memory device comprising:

a semiconductor substrate;
a first block;
a second block adjacent to the first block;
a main bitline;
a first auxiliary conductive region;
a first select transistor;
and a first select line,
wherein the first block comprises:
a first memory transistor having a first electrode, a second electrode and a gate electrode;
a first sub-bitline including a part functioning as the first electrode of the first memory transistor;
a second sub-bitline including a part functioning as the second electrode of the first memory transistor;
and
a first word line including a part functioning as the gate electrode of the first memory transistor,
while the second block comprises:
a second memory transistor having a third electrode, a fourth electrode and a gate electrode;
a third sub-bitline including a part functioning as the third electrode of the second memory transistor;
a fourth sub-bitline including a part functioning as the fourth electrode of the second memory transistor;
and
a second word line including a part functioning as the gate electrode of the second memory transistor,
and wherein the main bitline is electrically connected to the first auxiliary conductive region,
the second sub-bitline and the fourth sub-bitline are electrically connected to each other, thereby forming a common bitline, and
the first select transistor electrically connects selectively the electrically connected second and fourth sub-bitlines to the first auxiliary conductive region depending upon a potential on the first select line.

19 more elements

A semiconductor memory device comprising:

a semiconductor substrate;
a first block;
a second block adjacent to the first block;
a first main bitline;
a first auxiliary conductive region;
a first select transistor;
and a first select line,
wherein the first block comprises:
a first memory transistor having a first electrode, a second electrode and a gate electrode;
a first sub-bitline including a part functioning as the first electrode of the first memory transistor;
a second sub-bitline including a part functioning as the second electrode of the first memory transistor;
and
a first word line including a part functioning as the gate electrode of the first memory transistor,
while the second block comprises:
a second memory transistor having a third electrode, a fourth electrode and a gate electrode;
a third sub-bitline including a part functioning as the third electrode of the second memory transistor;
a fourth sub-bitline including a part functioning as the fourth electrode of the second memory transistor;
and
a second word line including a part functioning as the gate electrode of the second memory transistor,
and wherein the first main bitline is electrically connected to the first auxiliary conductive region,
the second sub-bitline and the fourth sub-bitline are electrically connected to each other, thereby forming a common bitline,
the first select transistor electrically connects selectively the electrically connected second and fourth sub-bitlines to the first auxiliary conductive region depending upon a potential on the first select line,
and wherein the first block further comprises:
a second select transistor having a fifth electrode comprising first and second parts, a sixth electrode and a gate electrode;
and
a second select line for activating the second select transistor,
and wherein a part of a fifth sub-bitline functions as the sixth electrode of the second select transistor,
a part of the first auxiliary conductive region functions as the first part of the fifth electrode of the second select transistor,
another part of the first auxiliary conductive region functions as the second part of the fifth electrode of the second select transistor, and
the second select transistor electrically connects selectively the first auxiliary conductive region to the fifth sub-bitline depending upon a potential on the second select line.

27 more elements

A semiconductor memory device comprising:

a first block;
a second block adjacent to the first block;
an auxiliary conductive region shared between the first block and the second block, and a main bitline electrically connected to the auxiliary conductive region;
and
wherein the first block comprises:
a first memory transistor having a first electrode, a second electrode and a gate electrode;
a first sub-bitline including a part functioning as the first electrode of the first memory transistor;
a second sub-bitline including a part functioning as the second electrode of the first memory transistor;
a second memory transistor having a third electrode, a fourth electrode and a gate electrode;
a third sub-bitline including a part functioning as the third electrode of the second memory transistor;
a fourth sub-bitline including a part functioning as the fourth electrode of the second memory transistor;
and
a first word line including a part functioning as the gate electrode of the first memory transistor and a part functioning as the gate electrode of the second memory transistor,
while the second block comprises:
a third memory transistor having a fifth electrode, a sixth electrode and a gate electrode;
a fifth sub-bitline including a part functioning as the fifth electrode of the third memory transistor;
a sixth sub-bitline including a part functioning as the sixth electrode of the third memory transistor;
a fourth memory transistor having a seventh electrode, an eighth electrode and a gate electrode;
a seventh sub-bitline including a part functioning as the seventh electrode of the fourth memory transistor;
an eighth sub-bitline including a part functioning as the eighth electrode of the fourth memory transistor;
and
a second word line including a part functioning as the gate electrode of the third memory transistor and a part functioning as the gate electrode of the fourth memory transistor,
wherein the first sub-bitline and the fifth sub-bitline are electrically connected to each other, thereby forming a common bit-line,
the fourth sub-bitline and the eighth sub-bitline are electrically connected to each other, thereby forming a common bit-line,
a first part of the auxiliary conductive region functions as a ninth electrode of a first select transistor,
a part of the electrically connected first and fifth sub-bitlines functions as a tenth electrode of the first select transistor,
a second part of the auxiliary conductive region functions as an eleventh electrode of a second select transistor, and
a part of the electrically connected fourth and eighth sub-bitlines functions as a twelfth electrode of the second select transistor.

25 more elements

Dependencies are inferred from the claim text.