US 5,852,317 AGranted

Method to reduce gate oxide damage due to non-uniform plasmas in read only memory arrays

AssigneeNational Semiconductor Corporation

InventorRina Berman

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Abstract

A common problem in the manufacture of MOS ROM devices is the "antenna effect", whereby charges accumulate on long conductors (especially gate poly) during certain processing steps, particularly plasma processing. These charges can cause gate voltage sufficient to punch-through or break down thin gate oxide regions. By adding a "load" transistor to each length of conductor (e.g., by bank or row), and adjusting the size of the load transistor to cause total capacitance on the conductor to reach a minimum value, the antenna effect is minimized and process yield is improved. The size of the load transistor is determined based upon the amount of program-dependent capacitive load placed on each conductor (i.e., the number of transistor gates connected to the conductor). One aspect of the invention provides for omitting the load transistor if there is no load on a conductor (i.e., no transistor gates connected), since in this case, there is essentially no likelihood of antenna-effect-induced damage to the transistor gates.

Claims29

Dependent claims

A method of reducing gate oxide damage in producing read-only-memory arrays, comprising:

providing a read-only-memory array, said array including a bank of MOS transistor sites corresponding, respectively, to one bit of storage in the read-only-memory array;
selectively enabling a first number of MOS transistors in said MOS transistor sites having respective gate terminals, each of such gate terminals providing access to a corresponding gate region having dimensions defining a first are, the first area characterized by a first value indicative of a size of the first area;
providing a long conductive line having dimensions defining a second area, the second area characterized by a second value indicative of a size of the second area;
connecting said long conductive line to said gate terminals;
providing a load transistor site at a selected position along said long conductive line for a load transistor having a gate terminal, said load transistor gate terminal providing access to a gate region of the load transistor, said gate region of the load transistor having dimensions defining a third area, the third area characterized by a third value indicative of a size of the third area;
calculating a mathematical relationship between the second value, indicative of the second area, of the conductive line, and the first value, indicative of the first area, for selectively enabled transistors
deciding whether to enable said load transistor at said load transistor site in response to the calculated mathematical relationship;
enabling said load transistor at said load transistor site only if it is decided in said deciding step to enable said load transistor;
and
connecting said load transistor gate terminal to said long conductive line.

7 more elements

A method of reducing gate oxide damage in producing read-only-memory arrays, comprising:

providing a read-only-memory array, said array including banks of MOS transistor sites, each such bank including a set of MOS transistor sites, each such MOS transistor site corresponding to one bit of storage in the read-only memory array;
for each bank, selectively enabling a number of MOS transistors in said MOS transistor sites in the bank, each selectively enabled transistor having a gate terminal providing access to a corresponding gate region having dimensions defining a first area, the first area characterized by a first value indicative of a size of the first area;
providing a long conductive line for each bank having dimensions defining a second area, the second area characterized by a second value indicative of a size of the second area;
connecting the long conductive line for each bank to the gate terminals of the enabled MOS transistors in the bank;
providing an associated load transistor site at a selected position along each long conductive line for a load transistor having an associated gate terminal, said load transistor gate terminal providing access to a gate region of the load transistor with which it is associated, each gate region of each load transistor having dimensions defining a third area, the third area characterized by a third value indicative of a size of the third area;
for each bank, calculating a mathematical relationship between the second value, indicative of the second area of the conductive line, and the first value, indicative of the first area, for selectively enabled transistors;
deciding whether to enable said load transistor at each load transistor site in response to the calculated mathematical relationship;
enabling said load transistor at said each load transistor site only if it is decided in said deciding step to enable said each load transistor;
and
connecting said load transistor gate terminal to said long conductive line with which its associated load transistor's site is associated.

7 more elements

Dependencies are inferred from the claim text.