Flash memory cell structure having a high gate-coupling coefficient and a select gate
AssigneeUnited Semiconductor Corp.
InventorsGary Hong, Patrick Wang, Wenchi Ting
Life of this patent
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Abstract
A flash memory cell structure comprising a semiconductor substrate having a first transistor and a second transistor formed thereon. The first transistor has a stacked gate and a first source/drain regions, wherein the stacked gate further includes a floating gate and a control gate. The control gate is formed above the floating gate. The second transistor is electrically connected in series with the first transistor. The second transistor functions as a select transistor and includes a gate and a second source/drain regions.
Claims8
A high gate-coupling coefficient flash memory cell structure comprising:
- a semiconductor substrate;
- a first transistor having a stacked gate and first source/drain regions above the semiconductor substrate, wherein the stacked gate includes a floating gate and a control gate, and that the control gate is formed above the floating gate, with the control gate and floating gate overlapping over an area about 3 micrometers long by 0.5 micrometers wide;
- and
- a second transistor having a gate and second source/drain regions electrically connected in series with the first transistor such that the second transistor functions as a select transistor.
A high gate-coupling coefficient flash memory cell structure comprising:
- a semiconductor substrate;
- a first transistor having a stacked gate and first source/drain regions above the semiconductor substrate, wherein the stacked gate includes a floating gate and a control gate, and that the control gate is formed above the floating gate;
- and
- a second transistor having a gate and second source/drain regions electrically connected in series with the first transistor such that the second transistor functions as a select transistor,
- wherein a channel width below the stacked gate is about 0.5 micrometer.
A high gate-coupling coefficient flash memory cell structure comprising:
- a semiconductor substrate;
- a first transistor having a stacked gate and first source/drain regions above the semiconductor substrate, wherein the stacked gate includes a floating sate and a control gate, and that the control gate is formed above the floating gate;
- and
- a second transistor having a gate and second source/drain regions electrically connected in series with the first transistor such that the second transistor functions as a select transistor,
- wherein a total width of the memory cell is about 3.5 micrometers.
Dependencies are inferred from the claim text.