Non-volatile memory devices including capping layer contact holes

Abstract

A non-volatile memory device includes a substrate having memory cell and peripheral circuit regions thereof. A non-volatile memory cell gate on a memory cell region of the substrate includes a floating gate on the substrate, a first insulating gate on the floating gate opposite the substrate, and a control gate on the first insulating layer opposite the floating gate. A resistor layer is provided on a peripheral circuit region of the substrate, and the second insulating layer is provided on the resistor layer opposite the substrate. In addition, a capping layer is provided on the second insulating layer opposite the resistor layer wherein a contact hole is defined by the second insulating layer and the capping layer thereby exposing a portion of the resistor layer. Related methods are also discussed.

Dependencies are inferred from the claim text.