Method for forming a multilevel interconnect structure of an integrated circuit by a single via etch and single fill process

A method for forming a multi-level interconnect structure having a first set of conductors electrically connected to a second set of conductors formed on a plane separate from the first set of conductors, comprising:

• depositing a first dielectric across a semiconductor topography having a first set of conductors arranged thereon;
• forming a barrier layer upon said first dielectric, said barrier layer having openings which extend through said barrier layer to expose said first dielectric in a region directly above a space which laterally separates a pair of said first set of conductors;
• forming a second dielectric only upon said openings to a thickness above said barrier layer;
• removing said barrier layer and said first dielectric at the outer periphery of said second dielectric directly above said first set of conductors to form at least one via;
• and
• forming a second set of conductors within said via, wherein at least two of said second set of conductors are laterally separated by said second dielectric.

A method for forming electrical connection between a first and a second set of conductors formed on separate elevational levels, comprising:

• providing a first dielectric upon a first set of conductors arranged upon a semiconductor topography;
• removing said first dielectric directly above said first set of conductors;
• depositing a second dielectric upon said first dielectric exclusively in a region directly above a space between a pair of said first set of conductors to form a fill site laterally bounded by said second dielectric;
• and
• forming a second set of conductors separated by said second dielectric by filling said fill site with a conductive material to an elevational level substantially equal to an upper surface of said second dielectric.