Method of manufacturing a shallow trench isolation for a semiconductor device
AssigneeMosel Vitelic, Inc.
InventorsChih-Hsun Chu, Ching-Nan Yang
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Abstract
A new method for forming shallow trench isolation is disclosed herein. A pad oxide layer and a silicon nitride layer are formed on a wafer, respectively. A plurality of trenches are created in the wafer. Then, a SAC layer is formed on an N-well. A BSG layer is formed on a P-well and the N-well. A thermal process is used to form a channel stop in the P-well. Then, the BSG layer and the SAC layer are removed. Subsequently, a LPD oxide layer is deposited in the trenches. Then, a CMP process is used to polish the LPD oxide layer for planarization. The pad oxide layer and the silicon nitride layer are removed. Next, a gate oxide layer is formed on the wafer.
Claims14
A method of forming a shallow trench isolation on a silicon wafer, a P-well and an N-well being formed in said silicon wafer, said method comprising:
- forming a pad layer on said silicon wafer;
- forming a silicon nitride layer on said pad layer;
- forming a plurality of trenches in said silicon wafer by etching said silicon nitride layer, said pad layer and said silicon wafer;
- forming a first sacrificial (SAC) oxide layer on the surface of said trenches and on the surface of said pad oxide layer;
- removing said first SAC oxide layer that is formed on said P-well;
- forming a BSG layer along the surface of said trenches, said BSG layer being on said pad oxide layer, said silicon nitride layer and said first SAC oxide layer;
- performing a thermal process for driving the boron ions that is in said BSG layer to diffuse into said P-well, therefore a channel stop layer being formed in said P-well;
- removing said BSG layer;
- removing said first SAC oxide layer;
- forming an oxide layer along the surface of said trenches and on the surface of said pad oxide layer;
- forming a liquid phase deposition (LPD) oxide layer in said trenches for isolation;
- performing a CMP process to remove a portion of said LPD oxide layer to the surface of said silicon nitride layer for planarization;
- removing said silicon nitride layer;
- and
- removing said pad oxide layer.
Dependencies are inferred from the claim text.