Method of forming a dram cell with a crown-fin-pillar structure capacitor

A method for manufacturing an integrated circuit capacitor, the method comprising the steps of:

• forming a first conductive layer over a semiconductor substrate;
• forming a composition layer that consists of alternating sublayers of BPSG sublayers and silicon dioxide sublayers on said first conductive layer;
• forming a contact hole in said composition layer and said first conductive layer;
• etching said composition layer through said contact hole using highly selective etching to etch said BPSG layers;
• forming a second conductive layer in said contact hole and over said composition layer;
• patterning a photoresist on said second conductive layer;
• etching said second conductive layer, composition layer and first conductive layer using said photoresist as an etching mask;
• stripping said photoresist;
• then
• forming a third conductive layer on said second conductive layer, said composition layer, and said first conductive layer;
• etching said third conductive layer and said second conductive layer to expose a top of said composition layer;
• removing said composition layer;
• forming a dielectric film on the surface of said first conductive layer, third conductive layer and said second conductive layer;
• and
• forming a forth conductive layer over said dielectric film.

A method of forming a crown shape polysilicon with a plurality of fins comprising the steps of:

• forming a first polysilicon layer on a substrate;
• forming a composition layer that consists of alternating BPSG layers and silicon dioxide layers on said first polysilicon layer;
• forming a hole through said composition layer and said first polysilicon layer to said substrate;
• using high selective etching to selectively etch said BPSG layers through said contact hole;
• forming a second polysilicon layer on said substrate, in said hole and over said composition layer;
• patterning a photoresist on said second polysilicon ayer;
• etching said second polysilicon layer, said composition layer and said first polysilicon layer using said photoresist as an etching mask;
• removing said photoresist;
• then
• forming a third polysilicon layer on said second polysilicon layer, said composition layer, and said first polysilicon layer;
• etching said third polysilicon layer, second polysilicon layer to expose a top layer of said composition layer;
• and
• removing said composition layer.