A method for manufacturing a ROM component having a silicon controlled rectifier structure, comprising the steps of:
- (a) providing a substrate having a planar surface and forming a first insulating layer over the planar surface;
- (b) forming in sequence, a heavily doped first type impurity layer, a lightly doped second type impurity layer and a lightly doped first type impurity layer over a surface of the first insulating layer;
- (c) processing the lightly doped first type impurity layer, the lightly doped second type impurity layer and the heavily doped first type impurity layer to form a plurality of generally parallel and separate strips of bit lines lying in a first direction;
- (d) forming a second insulating layer on the first insulating layer and on the bit lines;
- (e) removing part of the second insulating layer so that a remainder of the second insulating layer is leveled with the lightly doped first type impurity layer;
- (f) processing the lightly doped first type impurity layer and the lightly doped second type impurity layer of the bit lines to form a plurality of first contact windows in the bit lines;
- (g) forming a plurality of spacers on sidewalls of the first contact windows;
- (h) applying a first photoresist layer having a pattern to expose the first contact windows and part of the lightly doped first type impurity layer;
- (i) doping first type ions into the heavily doped first type impurity layer at a bottom of the first contact windows and an exposed portion of the lightly doped first type impurity layer, using the first photoresist layer and the spacers as masks, to form a plurality of first type diffusion regions and thereafter removing the first photoresist layer;
- (j) filling a first conducting layer into the first contact windows so that a top surface of the first conducting layer is leveled with the lightly doped first type impurity layer;
- (k) applying a second photoresist layer on the lightly doped first type impurity layer, the second photoresist layer having a pattern to expose part of the lightly doped first type impurity layer;
- (l) doping second type ions into an exposed portion of the lightly doped first type impurity layer, using the second photoresist layer as a mask, to form a plurality of second type diffusion regions, and thereafter removing the second photoresist layer to expose an intermediate top surface;
- (m) forming a third insulating layer over the intermediate top surface;
- (n) forming a plurality of second contact windows in the third insulating layer to expose the first conducting layer, the first type diffusion regions and part of the second type diffusion regions;
- (o) forming a second conducting layer on a surface of the third insulating layer such that the second conducting layer fills the second contact windows;
- and
- (p) forming in the second conducting layer a plurality of triggering word line electrodes above the first type diffusion regions, a plurality of common electrodes above the first conducting layer, and a plurality of generally parallel and separate strips of bit line electrodes lying in a second direction, so that the first and second directions cross each other at an angle.