Method for fabricating compact contactless trenched flash memory cell

A process for fabricating a compact contactless trenched flash memory array of a plurality of memory cells for semiconductor EEPROM devices, said process comprising the steps of:

• (a) forming a P-well in a wafer substrate;
• (b) growing a gate oxide layer over the P-well in the substrate, depositing a first polysilicon layer on the gate oxide layer and patterning said first polysilicon layer for forming deep trenches having the bottom thereof reaching down to said substrate, and then reoxidizing the processed substrate to seal a surface thereof;
• (c) depositing a first BPSG (borophosphosilicate glass) layer on said sealed substrate surface and then reflowing and etching back the first BPSG layer;
• (d) subsequently forming, on said reflowed first BPSG layer and said first polysilicon layer, an ONO (oxide-nitride-oxide) layer, depositing a second polysilicon layer with in-situ dope, forming a WSi.sub.x layer, growing a pad oxide layer, and then depositing a nitride layer;
• (e) forming stacked gates for said flash memory array by patterning into said formed nitride, pad oxide, WSi.sub.x, second polysilicon, and ONO layers, selectively etching back said first BPSG layer filled in said trenches, and then removing partially said first polysilicon and gate oxide layers from the substrate after said patterning;
• (f) forming n.sup.+ source/drain regions in the substrate between said stacked gates, and depositing sidewall spacers for said stacked gates;
• (g) depositing a third polysilicon layer over the substrate in process, followed by selectively etching back said third polysilicon layer to expose said stacked gate sidewall spacers, and then reducing resistance of said formed third polysilicon layer;
• (h) sealing edges of said stacked gates and a surface of said third polysilicon layer and then covering the third polysilicon layer and exposed stacked gates with a second BPSG layer;
• (i) forming contact openings for said source/drain regions;
• and
• (j) forming metal lines leading into said contact openings for interconnecting the memory cells in said flash memory array with peripheral control circuits of said semiconductor EEPROM devices.