US 5,851,873 AGranted

Method of making semiconductor memory device

AssigneeNippon Steel Semiconductor Corporation

InventorsIchiro Murai, Hidemi Arakawa, Shinobu Shigeta

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Abstract

A semiconductor memory device has a long refresh time and offers high reliability by minimizing junction leakage current, resulting in increased charge retention time. This is achieved by optimizing the diffusion layer junction depth formed in a deeper region of the semiconductor substrate which is in electrical contact with the impurity diffusion layer. Typically, junction depth is in excess of 0.1 .mu.m. Two methods for achieving such a structure are also provided. In one method, implantation voltage in excess of 80 KeV is used to implant P ions to form a high carrier concentration profile at a junction depth of greater than 0.1 .mu.m. In another method, implantation process are carried out in two steps so as to force the previously implanted ions deeper into the storage node electrode, and a subsequent heat treatment is carried out to further distribute the dopant ions into the substrate of the semiconductor substrate so as to disperse crystal defects into the substrate. The resulting structure is essentially free of crystal defects which cause current leakage from the boundary region between the dopant diffusion layer and the substrate in the conventional memory cell structure.

Claims6

Dependent claims

A method for making a semiconductor memory device provided with a memory capacitor having a storage node electrode in electrical contact with a dopant diffusion region through a contact hole, comprising the steps of:

forming dopant diffusion regions in a semiconductor substrate having a first conductivity type by ion implanting a dopant having a second conductivity type opposite in conductivity to said first conductivity type into said semiconductor substrate;
forming an interlayer isolator film on said semiconductor substrate;
opening said contact hole through said interlayer isolator film above one dopant diffusion region of said dopant diffusion regions;
forming a storage node electrode film having at least one portion extending through said contact hole to be in electrical contact with said one dopant diffusion region;
implanting second dopant ions of said second conductivity type into a top surface of said storage node electrode film followed by implanting driving dopant ions into said top surface to collide with the second dopant ions to force the second dopant ions to move deeper into said storage node electrode film to form a high concentration distribution profile;
and
subjecting said second ions forming said high concentration distribution profile to a heat treatment step so as to diffuse out some of said second ions forming said high concentration distribution profile from within said storage node electrode film into said semiconductor substrate so as to produce a junction depth of not less than 0.1 .mu.m for said at least one dopant diffusion region;
and
providing a dielectric layer and a cell plate electrode over the storage node electrode to form the memory capacitor.

6 more elements

Dependencies are inferred from the claim text.