US 5,851,872 AGranted

Method of fabricating dynamic random access memory

AssigneeUnited Microelectronics Corp.

InventorsHwi-Huang Chen, Gary Hong

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Abstract

A method of fabricating a DRAM which includes a capacitor and a metal oxide semiconductor field effect transistor. A field oxide layer is formed on a silicon substrate. A gate oxide layer is formed on the silicon substrate. A first polysilicon layer is deposited on the gate oxide layer. An insulator is deposited on the first polysilicon layer. A first silicon nitride layer is deposited on the insulator. The first silicon nitride layer, the insulator, the first polysilicon layer and the gate oxide layer are processed to form a gate electrode. First spacers are formed between the insulator and the substrate on sidewall on opposite sides of the gate electrode. Source-drain regions are formed on the substrate on the opposite sides of the gate electrode. A contact window is formed on the drain electrode. Second spacers are formed on surfaces of the first spacers which are adjacent to the contact window. A second silicon nitride layer is deposited on a surface of the first silicon nitride layer and a surface of the first spacers which are remote from the contact window. A second polysilicon layer is deposited on the contact window as a charge storage electrode of the capacitor. The first silicon nitride layer and the second silicon nitride layer are removed. A dielectric layer is deposited on the surface of the second polysilicon layer. A third polysilicon layer is deposited on the dielectric layer as the cell plate of the capacitor.

Claims16

Dependent claims

A method of fabricating dynamic random access memory that includes a capacitor and a metal oxide semiconductor field effect transistor, comprising the steps of

(a) forming a field oxide layer on a silicon substrate;
(b) forming a gate oxide layer on the silicon substrate;
(c) depositing a first polysilicon layer on the gate oxide layer;
(d) depositing an insulator on the first polysilicon layer;
(e) depositing a first silicon nitride layer on the insulator;
(f) processing the first silicon nitride layer, the insulator, the first polysilicon layer and the gate oxide layer to form a gate electrode having first and second sidewalls at respective opposite first and second sides thereof;
(g) forming first spacers on the first and second sidewalls;
(h) forming first and second source-drain regions on the substrate respectively beside the first and second sides of the gate electrode;
(i) forming a contact window on the first source-drain regions;
(j) forming a second spacer on a surface of the first spacer on the first sidewall, adjacent to the contact window;
(k) depositing a second silicon nitride layer on a surface of the first silicon nitride layer, and on the first spacer on the second sidewall;
(l) depositing a second polysilicon layer on the contact window, the second spacer, the first silicon nitride layer, and the second nitride layer, as a charge storage electrode of the capacitor;
(m) removing the first silicon nitride layer and the second silicon nitride layer;
(n) depositing a dielectric layer on the second polysilicon layer;
and
(o) depositing a third polysilicon layer on the dielectric layer as a cell plate of the capacitor.

13 more elements

Dependencies are inferred from the claim text.