Fabrication method for CMOS with sidewalls
AssigneeLG Semicon Co., Ltd.
InventorJeong-Hwan Son
Life of this patent
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Abstract
A semiconductor device and fabrication method therefor which improve device operation of a CMOS device. The semiconductor device and fabrication method therefor prevent the deterioration of short channel properties of a PMOS device and improve current driving capability of an NMOS device. The semiconductor device has halo impurity regions formed in either the NMOS region or the PMOS region such that a channel length of the PMOS device. Also, the source channel length of the PMOS device. Also, the source and drain regions of the PMOS device are prevented from forming deep source and drain regions, thus, preventing deterioration of the short channel properties for the PMOS device.
Claims44
A method of fabricating a semiconductor device, the method comprising the steps of:
- providing a substrate having a first region and a second region and a first gate structure and a second gate structure formed on the first region and the second region, respectively;
- forming first impurity regions in the first region on each side of the first gate structure;
- forming second impurity regions in the second region on each side of the second gate structure;
- forming first sidewalls on each side of the first gate structure and on each side of the second gate structure;
- forming third impurity regions in the second region on each side of the second gate structure from at least a portion of each of the second impurity regions;
- and
- forming fourth impurity regions adjacent to each of the first impurity regions in the first region and halo impurity regions adjacent to each of the second impurity regions in the second region.
A method of fabricating a semiconductor device, the method comprising the steps of:
- providing a substrate having a first region and a second region and a first gate structure and a second gate structure formed on the first region and the second region, respectively;
- forming first impurity regions in the first region on each side of the first gate structure;
- forming first sidewalls on each side of the first gate structure and on each side of the second gate structure;
- forming second impurity regions in the first region on each side of the first sidewalls of the first gate structure from at least a portion of each of the first impurity regions;
- forming second sidewalls on sides of the first sidewalls;
- forming third impurity regions in the second region on each side of the second sidewalls of the second gate structure;
- forming fourth impurity regions adjacent to each of the third impurity regions in the second region and halo impurity regions adjacent to each of the first impurity regions in the first region.
A method of fabricating a semiconductor device, the method comprising the steps of:
- providing a substrate having a NMOS region and a PMOS region;
- forming an NMOS gate structure and a PMOS gate structure on the NMOS region and the PMOS regions, respectively;
- forming an NMOS channel by forming N-type impurity regions in the NMOS region of the substrate on either side of the NMOS gate structure;
- forming a PMOS channel by forming P-type impurity regions in the PMOS region of the substrate on either side of the PMOS gate structure, the PMOS channel having a length which is greater than a length of the NMOS channel.
Dependencies are inferred from the claim text.