Semiconductor device

A method of fabricating a semiconductor device in which at least a first bipolar transistor having a vertical bipolar transistor structure, at least a second bipolar transistor having a vertical bipolar transistor structure, and at least a MOSFET are formed on a semiconductor substrate;

• said semiconductor device fabrication method comprising:
• (a) a first step of forming a collector layer of a first conductivity type of said first bipolar transistor, a collector layer of a second conductivity type of said second bipolar transistor, and an active region of a second conductivity type of said MOSFET;
• (b) a second step of forming a base diffusion layer of a second conductivity type in a region surrounded by said collector layer of said first bipolar transistor by implanting an impurity of a second conductivity type thereinto, and forming a diffusion layer of a second conductivity type in a region surrounded by said active region of said MOSFET by implanting an impurity of a second conductivity type thereinto, said second-conductivity-type base diffusion layer and said second-conductivity-type diffusion layer are formed simultaneously with each other by one-time ion-implantation of an impurity of a second conductivity type;
• (c) a third step of forming a base diffusion layer of a first conductivity type in a region surrounded by said collector layer of said second bipolar transistor by implanting an impurity of a first conductivity type thereinto and forming a channel dope diffusion layer of a first conductivity type which includes at-least a portion where a channel is to be formed in a region that is within said second-conductivity-type diffusion layer of said MOSFET by implanting an impurity of a first conductivity type thereinto, said first-conductivity-type base diffusion layer and said first-conductivity-type channel dope diffusion layer are formed simultaneously with each other by one-time ion-implantation of an impurity of a first conductivity type at a smaller implantation energy than an implantation energy used in said second step;
• and
• (d) a fourth step of forming a gate electrode on said region where said second-conductivity-type diffusion layer and said first conductivity-type channel dope diffusion layer are formed in said active region of said MOSFET, said fourth step being conducted subsequently to said third step.