High-voltage N-channel MOS transistor and associated manufacturing process
AssigneeSGS-Thomson Microelectronics S.A.
InventorsBruno Vajana, Livio Baldi
Life of this patent
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Abstract
A CMOS device and process are disclosed in which two types of N-channel MOS transistors are provided, one being formed in a P-well and one being formed outside the P-well where the relatively low doping concentration of P-type substrate serves as a channel defining region. This second type N-channel transistor an support higher junction voltages due to the lower p-type doping concentration than is possible for the first type N-channel transistor formed in the higher doping concentration P-well. A mask is provided to prevent boron doping in the substrate at the site of the high voltage transistor during the implantation step which defines the P-well.
Claims10
A CMOS memory device integrated on a substrate of semiconductor material having a first conductivity type, comprising:
- a first transistor having source and drain regions formed in a first portion of the substrate, the substrate defining junctions with said source and drain regions;
- a first well, having the first conductivity type, included in a second portion of the substrate to permit forming source and drain regions of a second transistor, said first well having a doping concentration greater than the doping concentration of the substrate and defining junctions with the source and the drain regions formed therein, wherein the first transistor can support a higher junction voltage than the second transistor;
- a second well, having a second conductivity type, included in a third portion of the substrate, to permit forming a third transistor therein of an opposite polarity from the first and second transistors;
- and
- wherein the source and drain regions of the first transistor comprise shallow, lightly doped portions and deep, heavily doped portions and wherein the shallow, lightly doped portions define edges of a channel of said first transistor.
A CMOS memory device integrated on a substrate of semiconductor material having a first conductivity type, comprising,
- a first transistor having source and drain regions formed in a first portion of the substrate, the substrate defining junctions with said source and drain regions;
- a first well, having the first conductivity type, included in a second portion of the substrate to permit forming source and drain regions of a second transistor, said first well having a doping concentration greater than the doping concentration of the substrate and defining junctions with the source and the drain regions formed therein, wherein the first transistor can support a higher junction voltage than the second transistor;
- a second well, having a second conductivity type, included in a third portion of the substrate, to permit forming a third transistor therein of an opposite polarity from the first and second transistors;
- and
- wherein the first and second transistors each comprise a respective gate insulator, the gate insulator of the first transistor being significantly thicker than the gate insulator of the second transistor.
A CMOS memory device integrated on a substrate of semiconductor material having a first conductivity type, comprising:
- a first transistor having source and drain regions formed in a first portion of the substrate, the substrate defining junctions with said source and drain regions;
- a first well, having the first conductivity type, included in a second portion of the substrate to permit forming source and drain regions of a second transistor, said first well having a doping concentration greater than the doping concentration of the substrate and defining junctions with the source and the drain regions formed therein, wherein the first transistor can support a higher junction voltage than the second transistor;
- a second well, having a second conductivity type, included in a third portion of the substrate, to permit forming a third transistor therein of an opposite polarity from the first and second transistors;
- and
- wherein the first transistor comprises a channel region that is disposed between the source and drain regions, at least one of the source and drain regions having a doping concentration that increases in a direction away from the channel region.
Dependencies are inferred from the claim text.