US 5,850,090 AGranted

Dynamic semiconductor memory device on SOI substrate

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorsToshiyuki Oashi, Takahisa Eimori

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Abstract

In a dynamic semiconductor memory device including a thin film SOI/MOSFET having a semiconductor layer on an insulator as an active region, an "L" level potential of a memory cell transistor, which connects/disconnects a capacitor for storing data as electric charges and a bit line for reading/writing data, is set at a fixed value higher than a ground potential and lower than a power supply potential, and a substrate bias is set at the ground potential. Even if isolation is carried out by LOCOS, sub-threshold leakage current due to a parasitic MOS in the vicinity of LOCOS edge can be suppressed because the potential of a word line is lower than that of the bit line when the memory cell transistor is in a cut-off state. Therefore, a dynamic semiconductor memory device including a thin film SOI/MOSFET which is immune to disturbing refresh can be achieved.

Claims4

Dependent claims

A dynamic semiconductor memory device, comprising:

first power supply means for supplying a ground potential;
second power supply means for supplying a predetermined potential higher than said ground potential;
a plurality of word lines the potentials of which are selectively pulled up from said ground potential to said predetermined potential;
a plurality of bit lines arranged to cross said plurality of word lines;
a memory cell array including a plurality of memory cells, each including an n-channel memory cell transistor having a source region, drain region and channel region formed in semiconductor layer on an insulator as an active region, each n-channel memory cell transistor further having a gate electrode above the channel region with an insulator layer therebetween, wherein the source region is connected to one of said bit lines and the gate electrode is connected to one of said word lines;
a sense amplifier for amplifying a potential change in accordance with stored data which is read out to said bit line corresponding to one memory cell of said memory cell array;
control means for controlling readout of data from said memory cell array and writing of data to said memory cell array;
pseudo ground level supply means for supplying a pseudo around level potential between said ground potential and said predetermined potential, to a line which provides a low level potential to each of said bit line and said memory cell;
driving means for driving said sense amplifier with said predetermined potential, said pseudo ground level potential and said ground level potential;
wherein said driving means supplies said predetermined potential and said ground level potential to said sense amplifier in a early stage of a driving operation for a predetermined period and supplies said predetermined potential and said pseudo ground level potential to said sense amplifier in a remainder of the driving operation;
and
whereby all of said n-channel memory cell transistors connected to unselected said word lines have the lower potential level of the gates than that of the sources.

9 more elements

A dynamic semiconductor memory device comprising:

an internal power supply circuit for generating an internal power supply potential based on an external power supply potential;
power supply means for supplying a predetermined potential lower than said internal power supply potential;
a plurality of word lines the potentials of which are selectively pulled down from said internal power supply potential to said predetermined potential;
a plurality of bit lines arranged to cross said plurality of word lines;
a memory cell array including a plurality of memory cells, each including a p-channel memory cell transistor having a source region, drain region and channel region formed in semiconductor layer on an insulator as an active region, each p-channel memory cell transistor further having a gate electrode above the channel region with an insulator layer therebetween, wherein the source region is connected to one of said bit lines and the gate electrode is connected to one of said word lines;
a sense amplifier for amplifying a potential change in accordance with stored data which is read out to said bit line corresponding to one memory cell of said memory cell array;
control means for controlling readout of data from said memory cell array and writing of data to said memory cell array;
pseudo power supply level means for supplying a pseudo power supply level potential between said predetermined potential and said internal power supply potential, to a line which provides a high level potential to each of said bit line and said memory cell;
driving means for driving said sense amplifier with said predetermined potential, pseudo power supply level potential and said internal power supply potential;
wherein said driving means supplies said predetermined potential and said internal power supply potential to said sense amplifier in a early stage of a driving operation for a predetermined period and supplies said predetermined potential and said pseudo power supply level potential to said sense amplifier in a remainder of a driving operation;
and
whereby all of said p-channel memory cell transistors connected to unselected said word lines have a higher potential level of a gates than that of a sources.

9 more elements

Dependencies are inferred from the claim text.