Teg for carrier lifetime evaluation

An evaluation pattern region for lifetime evaluation formed in a semiconductor substrate with first and second major surfaces, for evaluating carrier lifetime in said semiconductor substrate,

• wherein a first conductive layer of a first conductivity type and a second conductive layer of a second conductivity type, different from said first conductivity type, provide said first and second major surfaces, respectively,
• said first conductive layer comprising:
• an electrode region with relatively high impurity concentration, said electrode region selectively formed in a surface portion on a side of said first major surface;
• and
• a connecting region with relatively low impurity concentration, for connecting said electrode region and said second conductive layer,
• wherein an area ratio between said electrode region at said first major surface and a portion functioning for said electrode region at said second major surface is determined so that said voltage values get isolated from each other in simulation of evaluating said carrier lifetime by obtaining voltage values at a reference current value for respective plurality of discrete values representing said carrier lifetime as a parameter.