Integrated circuit design system and method for generating a regular structure embedded in a standard cell control block

A method for generating a standard cell control block design, comprising the steps of:

• generating a net list representative of a plurality of elements;
• calculating an absolute physical position on a wafer die for at least one element of said plurality of elements of said net list;
• modifying said net list by adding said position to said net list as a special property associated with said at least one element;
• applying a placement and routing algorithm to said modified net list so that said at least one element is placed at said position;
• and
• preventing said placement and routing algorithm from repositioning said at least one element from said absolute physical position provided by said special property.

A system for generating an optimized design of a standard cell control block having a regular structure is embedded therein, the system comprising:

• a special class mechanism for creating a special class of cells within said net list that comprises cells associated with said regular structure that are embedded in said standard cell control block, each said cell in said special class having a special property designating an absolute physical position on a wafer die for that said cell;
• whereby said special class mechanism modifies said net list so that a placement and routing algorithm can process said modified net list to generate an optimum design for said standard cell control block;
• and
• wherein said placement and routing algorithm is prevented from repositioning cells in said special class from said absolute physical positions provided by said special property.