Structure and method of forming vias
AssigneeSTMicroelectronics S.r.l.
InventorsFusen E. Chen, Fu-Tai Liou, Girish A. Dixit
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AssigneeSTMicroelectronics S.r.l.
InventorsFusen E. Chen, Fu-Tai Liou, Girish A. Dixit
Estimating the term…
A method is provided for forming a contact opening or via of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first metal region is formed over an underlying region. A first insulating layer is formed over the integrated circuit. A second insulating layer is then formed over the first insulating layer. A portion of the second insulating layer is etched to expose a portion of the first insulating layer wherein the exposed first insulating layer and the remaining second insulating layer form a substantially planar surface. A metal oxide layer is formed over the exposed first insulating layer and the remaining second insulating layer. A photoresist layer is formed and patterned over the metal oxide layer. The metal oxide layer is then selectively etched to form a via exposing a portion of the first insulating layer. The first insulating layer in the via is then selectively etched to expose a portion of the first metal region. The photoresist layer is removed and a second metal layer is then formed over the metal oxide layer and in the via contacting the first metal region.
A contact structure between two conducting portions of an integrated circuit device, comprising:
A contact structure between two conducting portions of an integrated circuit device, comprising:
A structure consisting of a portion of a semiconductor integrated circuit, comprising:
Dependencies are inferred from the claim text.