Multiple node ESD devices
AssigneeIntegrated Device Technology, Inc.
InventorsChuen-Der Lien, Paul Y. M. Shy
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Abstract
An ESD protection device is provided which reduces the layout area required, utilizing multiple-node configurations and multiple node electrical couplings.
Claims14
An electrostatic discharge protection device for an integrated circuit device including a first voltage rail, a second voltage rail and a pad, said electrostatic discharge protection device comprising:
- a first region of semiconductor material of a first conductivity type;
- a second region of semiconductor material of a second conductivity type extending into said first region from a surface of said first region, said second region being connected to said pad;
- a third region of semiconductor material of said second conductivity type extending into said first region from said surface, said third region being connected to said first voltage rail;
- a fourth region of semiconductor material of said second conductivity type extending into said first region of semiconductor material from said surface, said fourth region being positioned between said second and third regions such that a first channel is defined by said semiconductor material of said first conductivity type located between said second region and said fourth region, and a second channel is defined by said semiconductor material of said first conductivity type located between said third region and said fourth region, said fourth region being connected to said second voltage rail;
- a first gate positioned above said first channel;
- and
- a second gate positioned above said second channel.
An electrostatic discharge protection device for an integrated circuit device including a first voltage rail, a second voltage rail, and a pad, said electrostatic discharge protection device comprising:
- a first region of semiconductor material of a first conductivity type;
- a plurality of regions of semiconductor material of a second conductivity type extending into said first region from a surface of said first region, said plurality of regions of second conductivity type being spaced apart to define a channel region in said semiconductor material of said first conductivity type between adjacent ones of said plurality of regions;
- and
- a plurality of gates, each of said gates being positioned above an associated one of said channel regions,
- wherein a first set of said regions of second conductivity type material is connected to said first voltage rail, a second set of said regions of second conductivity type material is connected to said second voltage rail and a third set of said regions of said second conductivity type material is connected to said pad, and
- wherein predetermined ones of said second conductivity type regions connected to said pad are positioned between said second conductivity type regions connected to said first voltage rail.
An electrostatic discharge protection device for an integrated circuit device including first, second and third pads defining first, second and third electrical nodes, respectively, said electrostatic discharge protection device comprising:
- a first region of semiconductor material of a first conductivity type;
- a second region of semiconductor material of a second conductivity type extending into said first region from a surface of said first region, said second region being connected to said first electrical node;
- a third region of semiconductor material of said second conductivity type extending into said first region from said surface, said third region being connected to said second electrical node;
- a fourth region of semiconductor material of said second conductivity type extending into said first region of semiconductor material from said surface, said fourth region being positioned between said second and third regions such that a first channel is defined by said semiconductor material of said first conductivity type located between said second region and said fourth region, and a second channel is defined by said semiconductor material of said first conductivity type located between said third region and said fourth region, said fourth region being connected to said third electrical node;
- a first gate positioned above said first channel;
- and
- a second gate positioned above said second channel.
Dependencies are inferred from the claim text.