Methods for metal etching with reduced sidewall build up during integrated circuit manufacturing

In a plasma processing chamber, a method for reducing sidewall polymer buildup during etching through a selected portion of a layer stack, said layer stack comprising a bottom barrier layer, a metallization layer disposed above said bottom barrier layer, a top barrier layer disposed above said metallization layer, and a photoresist layer disposed above said metallization layer, comprising:

• etching at least partially through said top barrier layer using a first chamber pressure;
• etching at least partially through said metallization layer using a second chamber pressure higher than said first chamber pressure, wherein said first chamber pressure is configured to cause said top barrier layer to be etched with a higher sputter component than a sputter component associated with said second chamber pressure;
• and
• etching at least partially through said bottom barrier layer using a third chamber pressure lower than said second chamber pressure, wherein said third chamber pressure is configured to cause said bottom barrier layer to be etched with a higher sputter component than said sputter component associated with said second chamber pressure.