Method of manufacturing non-volatile semiconductor memory having erasing gate

A method of a semiconductor memory device comprising the steps of:

• selectively forming a first conductive layer on a first insulating layer covering a semiconductor substrate;
• covering said first conductive layer with a second insulating layer;
• forming first and second control gates on said second insulating layer separately from each other;
• covering said first and second control gates with third and fourth insulating layers, respectively;
• selectively removing said first conductive layer by use of said third and fourth insulating layers as a mask to form first and second floating gates, each of said first and second floating gates thereby having an exposed side surface;
• forming first and second tunnel insulating films on the exposed side surfaces of said first and second floating gates, respectively;
• forming a second conductive layer to cover said first to fourth insulating layers and to fill a space between said first and second tunnel insulating films;
• etching back said second conductive layer until top surfaces of said third and fourth insulating layers are exposed, a first part of said second conductive layer being thereby left in contact with said first and second tunnel insulating films to serve as a erasing gate and a second part of said second conductive layer being left in contact with said second insulating film
• covering said erasing gate with a mask layer;
• and
• removing said second part of said second conductive layer by use of said mask layer as a mask.

A method of manufacturing a non-volatile semiconductor memory, comprising the steps of;

• forming a floating gate on a first region of a semiconductor substrate having said first region and a second region,
• forming a dielectric film on said floating gate,
• forming a first conductive film on the entire surface of said first region and said second region,
• selectively etching said first conductive film thereby to form a gate of a transistor over said second region and a control gate over said dielectric film,
• forming said walls on both sides of said control gate,
• forming a tunnel dielectric film adjacent to said floating gate,
• forming a second conductive film on the entire surface of said first region and said second region,
• etching back said second conductive film by an amount almost equal to the thickness of said second conductive film to remove said second conductive film from said second region and make an erasing gate adjacent to said tunnel dielectric film,
• covering said erasing gate and said transistor with a mask, and
• removing said second conductive film remaining in the regions outside said mask.