Method of making buried contact in DRAM technology

A method of forming a buried contact in a semiconductor substrate in the fabrication of an integrated circuit comprising:

• providing word lines over the surface of said semiconductor substrate;
• depositing a first insulating layer overlying said word lines;
• etching away said first insulating layer where it is not covered by a buried contact mask to provide an opening to said semiconductor substrate;
• depositing a dielectric layer over said first insulating layer and over said semiconductor substrate within said opening;
• anisotropically etching said dielectric layer to leave dielectric spacers on the sidewalls of said word lines and on the sidewalls of said first insulating layer;
• depositing a first layer of polysilicon overlying said first insulating layer and over said substrate within said opening;
• doping said first polysilicon layer with dopant;
• driving in said dopant to form a buried contact junction within said semiconductor substrate under said opening;
• patterning said first polysilicon layer to form a polysilicon contact overlying said buried contact junction wherein the mask used for said patterning is misaligned and wherein a portion of a dielectric spacer overlying said buried contact junction is exposed and wherein a portion of said first polysilicon layer other than that of the contact remains as residue;
• and
• etching away said first polysilicon layer residue wherein said exposed dielectric spacer protects said buried contact junction within said semiconductor substrate from said etching completing the formation of said buried contact in the fabrication of an integrated circuit.

A method of forming a buried contact in a semiconductor substrate in the fabrication of a dynamic random access memory (DRAM) integrated circuit comprising:

• providing word lines over the surface of said semiconductor substrate;
• depositing a first insulating layer overlying said word lines;
• etching away said first insulating layer where it is not covered by a buried contact mask to provide an opening to said semiconductor substrate;
• depositing a dielectric layer over said first insulating layer and over said semiconductor substrate within said opening;
• anisotropically etching said dielectric layer to leave dielectric spacers on the sidewalls of said word lines and on the sidewalls of said first insulating layer;
• depositing a first layer of polysilicon overlying said first insulating layer and over said substrate within said opening;
• doping said first polysilicon layer with dopant;
• driving in said dopant to form a buried contact junction within said semiconductor substrate under said opening;
• patterning said first polysilicon layer to form a polysilicon contact overlying said buried contact junction wherein said patterning also forms a capacitor electrode and wherein the mask used for said patterning is misaligned and wherein a portion of a dielectric spacer overlying said buried contact junction is exposed and wherein a portion of said first polysilicon layer other than that of the contact remains as residue;
• etching away said first polysilicon layer residue wherein said exposed dielectric spacer protects said buried contact junction within said semiconductor substrate from said etching;
• depositing a capacitor dielectric layer overlying said patterned first polysilicon layer;
• depositing a second polysilicon layer overlying said capacitor dielectric layer;
• and
• patterning said second polysilicon layer to form a capacitor top plate completing the formation of said buried contact in the fabrication of said DRAM integrated circuit.