Static memory device including supplemental gate capacitance

A static semiconductor memory device for receiving power from a first power line and a second power line located apart from each other, said device comprising:

• a semiconductor substrate;
• first and second load transistors located over said semiconductor substrate parallel to each other, along said first power line and connected to said first power line, each of said first and second load transistors having a gate and a drain;
• first and second drive transistors located over said semiconductor substrate parallel to each other, along said second power line and connected to said second power line, each of said first and second drive transistors having a gate and a drain;
• a pair of bit lines crossing said first and second power lines and running substantially parallel to each other;
• first and second select transistors respectively connected to said pair of bit lines, each of said first and second select transistors having a drain;
• a first connection line for commonly connecting said gate of said first load transistor and said gate of said first drive transistor to said drains of said second load transistor, said second drive transistor and said first select transistor;
• a second connection line for commonly connecting said gate of said second load transistor and said gate of said second drive transistor to said drains of said first load transistor, said first drive transistor and said second select transistor;
• and
• a capacitor connected between either of said first connection line or said second connection line and said semiconductor substrate.