Single poly devices for monitoring the level and polarity of process induced charging in a MOS process
AssigneeIntel Corporation
InventorsMohsen Alavi, Payman Aminzadeh, Robert A. Gasser, Sunit Tyagi, Gilroy J. Vandentop
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Abstract
A monitoring device to monitor process induced charge employing a single layer of polysilicon forming a floating gate. The device comprises two capacitors, one for charging and the other for discharging a floating gate of an n-channel transistor. Embodiments which permit the monitoring of positive charge, negative charge and both positive and negative charge are described. The device is reusable and lends itself to in-line monitoring as opposed to some prior art devices used for end-of-line monitoring.
Claims6
A device formed in a wafer for providing data on electrostatic charge build-up that the wafer is subjected to, comprising:
- a transistor of a first conductivity type having an electrically floating gate;
- a first and second electrically floating well of a first conductivity type formed in the wafer;
- a first capacitor structure defined by at least one region of a second conductivity type formed in the first well and the gate of the first transistor extending over the first well;
- a second capacitor structure defined by at least one second region of a second conductivity type formed in the second well and the gate extending over the second well;
- and
- at least one antenna for collecting charge coupled to the first and second regions.
A device formed in a wafer for providing data on electrostatic charge build-up that the wafer is subjected to, comprising:
- a transistor of a first conductivity type having an electrically floating gate;
- a first and second well of a first conductivity type formed in the wafer;
- a first capacitor structure defined by at least one first region of a second conductivity type formed in the first well and the gate of the first transistor extending over the first well, the first region being electrically coupled to the first well;
- a second capacitor structure defined by at least one second region of a second conductivity type formed in the second well and the gate extending over the second well, the second region being electrically coupled to the second well;
- and
- at least one antenna for collecting charge coupled to the first and second regions.
A device formed in a wafer for providing data on electrostatic charge build-up that the wafer is subjected to, comprising:
- a transistor of a first conductivity type having an electrically floating gate formed in a substrate region;
- a first and second well of a first conductivity type formed in the wafer, the first and second wells being electrically connected to one another and the substrate region;
- a first capacitor structure defined by at least one first region of a second conductivity type formed in the first well and the gate of the first transistor extending over the first well;
- a second capacitor structure defined by at least one second region of a second conductivity type formed in the second well and the gate extending over the second well;
- and
- at least one antenna for collecting charge coupled to the first and second regions.
Dependencies are inferred from the claim text.