Flash memory device and manufacturing method therefor

A flash memory device comprising:

• a semiconductor substrate of a first conductive type;
• a field insulating layer buried in a trench formed on said semiconductor substrate of a first conductive type in order to define an active region;
• a tunnel insulating film formed on said active region;
• first and second conductive layers which are patterned to define a plurality of floating gates which extend on said tunnel insulating film and said field insulating layer;
• an insulating layer formed on said second conductive layer;
• a third conductive layer for a control gate formed on said insulating layer;
• a first impurity layer for cell channel stop regions formed of impurities of a first conductive type in said semiconductor substrate, said channel stop regions extending between said floating gates formed on said tunnel insulating film;
• and
• a second impurity layer for a source/drain region of a select transistor of a second conductive type, opposite to said first conductive type, in said semiconductor substrate, said source/drain region of the select transistor extending between said floating gates formed on said field insulating layer.

A flash memory device comprising:

• a semiconductor substrate of a first conductive type;
• a field insulating layer buried in a first trench formed in said semiconductor substrate of a first conductive type in order to define an active region;
• a tunnel insulating film formed on said active region;
• first and second conductive layers which are patterned to define a plurality of floating gates which extend on said tunnel insulating film and said field insulating layer;
• an insulating layer formed on said second conductive layer;
• a third conductive layer for a control gate formed on said insulating layer;
• a first impurity layer for cell channel stop regions formed of impurities of a first conductive type in a lower portion of a second trench formed by etching said semiconductor substrate between adjacent ones of said floating gates formed on said tunnel insulating layer;
• and
• a second impurity layer for a source and drain of a select transistor formed of a second conductive type, opposite to said first conductive type, in said semiconductor substrate between respective floating gates formed on said field insulating layer.