EEPROM cell having reduced capacitance across the layer of tunnel oxide
AssigneeNational Semiconductor Corporation
InventorMax C. Kuo
Life of this patent
Estimating the term…
Abstract
The capacitance across the layer of tunnel oxide in an electrically-erasable programmable read-only-memory (EEPROM) cell is reduced by forming the layer of tunnel oxide to have a first region which is substantially thicker than a second region. The thicker region of tunnel oxide results from doping the buried region exposed by the tunnel window so that the buried region has different levels of dopant concentration. When the tunnel oxide is then grown over the buried region, the oxide formed over the more heavily doped portion grows at a faster rate than does the portion with the lower dopant concentration.
Claims19
An electrically-erasable programmable read-only-memory (EEPROM) cell formed in a substrate of a first conductivity type, the EEPROM cell comprising:
- spaced-apart buried regions formed in the substrate, the buried regions having a first concentration of a second conductivity type;
- spaced-apart oxide regions formed over the buried regions so that an oxide region is formed over each buried region, one of the oxide regions having a tunnel window that exposes a portion of the buried region underlying said one of the oxide regions, said portion of the buried region having a first area and a second area, the first area of said portion of the buried region having a dopant concentration higher than the second area of said portion of the buried region;
- a layer of cell rate oxide formed over the substrate between the oxide regions;
- and
- a layer of tunnel oxide formed over said portion of the buried region so that the layer of tunnel oxide formed over the first area is thicker than the layer of tunnel oxide formed over the second area.
A memory cell formed in a substrate of a first conductivity type, the cell comprising:
- a first region of a second conductivity type formed in the substrate;
- a second region of the second conductivity type formed in the substrate, the second region being spaced-apart from the first region and having a first surface region, a second surface region, and a third surface region;
- a first dielectric having a first thickness and contacting the first surface region;
- a second dielectric having a second thickness and contacting the second surface region, the second thickness being greater than the first thickness, the second dielectric contacting the first dielectric;
- and
- a third dielectric having a third thickness and contacting the third surface region, the third thickness being greater than the second thickness, the third dielectric contacting the first and second dielectrics.
A memory cell formed in a substrate of a first conductivity type, the cell comprising:
- a first region of a second conductivity type formed in the substrate;
- a second region of the second conductivity type formed in the substrate, the second region being spaced-apart from the first region and having a first surface region, a second surface region contacting the first surface region, and a third surface region contacting the first and second surface regions;
- a dielectric layer contacting the second region and having a plurality of thicknesses such that the dielectric layer formed over the first surface region has a first thickness, the dielectric layer formed over the second surface region has a second thickness, and the dielectric layer formed over the third surface region has a third thickness, the second thickness being greater than the first thickness, the third thickness being greater than the second thickness.
A memory cell formed in a substrate of a first conductivity type, the cell comprising:
- spaced-apart conductive regions formed in the substrate, the conductive regions having a first concentration of a second conductivity type;
- spaced-apart first insulation regions formed over the conductive regions so that a first insulation region is formed over each conductive region, one of the first insulation regions having a tunnel window that exposes a portion of a conductive region underlying said one of the first insulation regions, said portion of the conductive region having a first area and a second area, the first area of said portion of the conductive region having a dopant concentration higher than the second area of said portion of the conductive region;
- a first layer of insulation formed over the substrate between the conductive regions;
- and
- a second layer of insulation formed over said portion of the conductive region so that the second layer of insulation formed over the first area is thicker than the second layer of insulation formed over the second area.
Dependencies are inferred from the claim text.