Vertical conduction MOS controlled thyristor with increased IGBT area and current limiting
AssigneeInternational Rectifier Corporation
InventorsDaniel M. Kinzer, Weizuo Zhang
Life of this patent
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Abstract
An MCT is formed as a four-layer device, using alternating cells of: (a) P diffusions in an N.sup.- wafer having lower N.sup.+ and P.sup.+ layers with N.sup.+ cathode regions in the P diffusions, and (b) shallow P.sup.+ diverter cells. A cathode electrode is connected to the N.sup.+ cathodes, but not to the P diffusions containing the N.sup.+ cathode regions. The alternating cells are arranged in checkerboard fashion with the cells of any given row having a narrow spacing to define a narrow turn-off channel and the rows being more widely spaced to define a conduction channel having a reduced inherent JFET resistance.
Claims14
A four-layer MCT device comprising a thin chip of silicon having a bottom layer of P.sup.+ concentration, a layer of N.sup.+ concentration above said bottom layer, an N.sup.- body layer above said N.sup.+ layer, a plurality of first spaced cells each including a P type channel diffusion formed in said N.sup.- body layer and an N.sup.+ cathode diffusion region received in said P type channel diffusion;
- a plurality of second spaced cells each including a P.sup.+ diffusion;
- and a cathode electrode connected to said N.sup.+ cathode diffusions and insulated from said P type channel diffusions;
- said first spaced cells being interspersed with said second spaced cells in a checkerboard pattern that includes spaced rows which are each comprised of alternating first and second spaced cells;
- the distance between adjacent ones of said spaced rows being treater than the distance between adjacent ones of said first and second spaced cells within a respective row.
Dependencies are inferred from the claim text.