US 5,843,817 AGranted

Process for integrating stacked capacitor DRAM devices with MOSFET devices used for high performance logic circuits

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsJin-Yuan Lee, Mong-Song Liang

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Abstract

A semiconductor fabrication process has been developed in which both stacked capacitor DRAM, and MOSFET logic device structures, are integrated on a single silicon chip. The process features combining process steps for both device types. A single dielectric layer is used as a capacitor dielectric layer, for a stacked capacitor DRAM device, and as a gate insulator layer for a MOSFET logic device. In addition a specific polysilicon layer is used for formation of the upper polysilicon electrode, for the stacked capacitor DRAM device, as well as use for formation of the polysilicon gate structure, for the MOSFET logic device. A specific anneal cycle is used to reduce charges in the stacked capacitor DRAM device, while a less severe anneal cycle is used with the shallow junction MOSFET logic device.

Claims20

Dependent claims

A method for fabricating a memory device, and a logic device, on the same single semiconductor chip, using an integrated fabrication process, comprising the steps of:

forming field oxide regions in a semiconductor substrate;
forming a first polysilicon gate structure, on a first gate insulator layer, in a first region of the semiconductor substrate, to be used for said memory device;
forming a first lightly doped source and drain region, in said first region of said semiconductor substrate, in an area not covered by said first polysilicon gate structure;
forming first insulator spacers, on sides of said first polysilicon gate structure;
forming a first heavily doped source and drain region in said first region of said semiconductor substrate, in an area not covered by said first insulator spacers, and not covered by said first polysilicon gate structure;
performing a first anneal cycle;
depositing an interlevel dielectric layer;
opening a contact hole in said interlevel dielectric layer, exposing said first heavily doped source and drain region, in said first region of said semiconductor substrate;
forming a lower polysilicon electrode structure, contacting said first heavily doped source and drain region, in said first region of said semiconductor substrate;
removing said interlevel dielectric layer, a first polysilicon layer, and said gate insulator layer, from a second region of said semiconductor substrate, to be used for said logic device;
growing an insulator layer on the exposed surface of said lower polysilicon electrode structure, in said first region of said semiconductor substrate, to be used as a capacitor dielectric layer for said memory device, and growing said insulator layer on the surface of said second region of said semiconductor substrate, exposed between field oxide regions, to be used as a second gate insulator layer for said logic device;
deposition and patterning of a polysilicon layer, forming an upper polysilicon electrode structure, overlying said capacitor dielectric layer, and said lower polysilicon electrode structure, in said first region of said semiconductor substrate, and forming a second polysilicon gate structure, on said second gate insulator layer, in said second region of said semiconductor substrate;
forming a second lightly doped source and drain region in said second region of said semiconductor substrate, in an area not covered by said second polysilicon gate structure;
forming second insulator spacers on the sides of said second polysilicon gate structure;
forming a second heavily doped source and drain region in said second region of said semiconductor substrate, in an area not covered by said second polysilicon gate structure, and not covered by said second insulator spacers;
and
performing a second anneal cycle.

14 more elements

A method for fabricating a stacked capacitor DRAM device, and a MOSFET logic device, on the same semiconductor chip, using an integrated fabrication process, comprising the steps of:

forming field oxide regions in a semiconductor substrate;
growing a first gate insulator layer on an area of said semiconductor substrate, to be used as the gate insulator for said stacked capacitor DRAM device;
depositing a first polysilicon layer;
patterning of said first polysilicon layer to create a first polysilicon gate structure, on said first gate insulator layer, for stacked capacitor DRAM structure;
forming a first lightly doped source and drain region, for said stacked capacitor DRAM device, in an area of said semiconductor substrate not covered by said first polysilicon gate structure;
forming first insulator spacers on the sides of said first polysilicon gate structure;
forming a first heavily doped source and drain region, for stacked capacitor DRAM device, in an area of said semiconductor substrate not covered by said first polysilicon gate structure, and not covered by said first insulator spacers;
performing a first anneal cycle;
depositing an interlevel dielectric layer;
opening a storage node contact hole in said interlevel dielectric layer, exposing said first heavily doped source and drain region;
depositing a second polysilicon layer;
patterning of said second polysilicon layer, creating a polysilicon storage node electrode, for said stacked capacitor DRAM device, contacting said first heavily doped source and drain region;
removing said interlevel dielectric layer from a region of said semiconductor substrate to be used for said MOSFET logic device;
forming a dielectric layer on the surface of said polysilicon storage node electrode, to be used as a capacitor dielectric layer for said stacked capacitor DRAM device, and forming said dielectric layer on the surface of said semiconductor substrate, to be used as a second gate insulator layer, for said MOSFET logic device;
depositing a third polysilicon layer;
patterning of said third polysilicon layer, creating an upper polysilicon electrode, for said stacked capacitor DRAM device, and creating a second polysilicon gate structure for said MOSFET logic device;
forming a second lightly doped region, for said MOSFET logic device, in an area of said semiconductor substrate not covered by said second polysilicon gate structure;
forming second insulator spacers on sides of said second polysilicon gate structure;
forming a second heavily doped source and drain region, for said MOSFET logic device, in an area of said semiconductor substrate not covered by said second insulator spacers, and not covered by said second polysilicon gate structure;
and
performing a second anneal cycle.

18 more elements

Dependencies are inferred from the claim text.