Method of making a PMOSFET in a semiconductor device
AssigneeGoldstar Electron Co., Ltd.
InventorHyunsang Hwang
Life of this patent
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Abstract
An improved p+ polysilicon gated PMOSFET having a channel on the surface of a silicon substrate and improved short channel behavior is disclosed. A simplified process allows making a p+ doped gate and source/drain regions at the same time, the transistor particularly having a stable threshold voltage. The disclosed method provides the steps of: (A) forming an active region and an insulation region on an n-type semiconductor substrate; growing a gate insulating layer on the silicon substrate; depositing a polysilicon layer on the gate insulating layer; annealing the polysilicon layer in the presence of NH.sub.3 or other nitrogen-containing gas; (C) forming a gate line by patterning and etching the polysilicon layer; and (D) implanting BF.sub.2 ions into the semiconductor substrate.
Claims19
A method of forming a doped polysilicon layer in a semiconductor device, comprising the steps of:
- (A) forming a polysilicon layer having grain boundaries on a semiconductor substrate;
- (B) annealing the polysilicon layer in the presence of NH.sub.3, wherein the annealing is conducted under conditions wherein a silicon-nitrogen material is formed at the grain boundaries of the polysilicon layer;
- and
- (C) doping boron ions into the polysilicon layer by ion implantation, wherein the silicon-nitrogen material formed at the grain boundaries inhibits diffusion of the boron ions along the grain boundaries.
A method of manufacturing a PMOSFET in a semiconductor device, comprising the steps of:
- (A) forming an active region and an insulation region on an n-type semiconductor substrate, and forming a gate insulating layer on the semiconductor substrate;
- (B) depositing a polysilicon layer having grain boundaries on the gate insulating layer, and annealing the polysilicon layer in the presence of NH.sub.3, wherein the annealing is conducted under conditions wherein a silicon-nitrogen material is formed at the grain boundaries of the polysilicon layer;
- (C) forming a gate line by patterning and etching the polysilicon layer;
- and
- (D) implanting boron ions comprising BF.sub.2 ions into the semiconductor substrate, wherein the silicon-nitrogen material formed at the grain boundaries inhibits diffusion of the boron ions along the grain boundaries.
A method of manufacturing a PMOSFET in a semiconductor device, comprising the steps of:
- (A) forming an active region and an insulation region on an n-type semiconductor substrate, and growing a gate insulating layer on the semiconductor substrate:
- (B) depositing a polysilicon layer having grain boundaries on the gate insulating layer, and forming a gate line by patterning the polysilicon layer;
- (C) annealing the polysilicon layer in the presence of NH.sub.3, wherein the annealing is conducted under conditions wherein a silicon-nitrogen material is formed at the grain boundaries of the polysilicon layer;
- and
- (D) implanting boron ions comprising BF.sub.2 ions into a surface of the semiconductor substrate, wherein the silicon-nitrogen material formed at the grain boundaries inhibits diffusion of the boron ions along the grain boundaries.
A method of manufacturing a PMOSFET in a semiconductor device, comprising the steps of:
- (A) forming a gate insulating layer on an n-type semiconductor substrate;
- (B) depositing a polysilicon layer having grain boundaries on the gate insulating layer, and annealing the polysilicon layer in the presence of NH.sub.3, wherein the annealing is conducted under conditions wherein a silicon-nitrogen material is formed at the grain boundaries of the polysilicon layer;
- (C) forming a gate electrode by patterning the polysilicon layer;
- and
- (D) implanting impurity ions into the semiconductor substrate, wherein the silicon-nitrogen material formed at the grain boundaries inhibits diffusion of the boron ions along the grain boundaries.
Dependencies are inferred from the claim text.