Method of making an insulated gate bipolar transistor with high-energy P+ i m

In a method of making an insulated gate switching transistor having a layer of one conductivity type, with a surface, a first well of opposite conductivity type to said one conductivity type in said surface, an annular second well of said one conductivity type disposed in said surface concentrically within said first well, and an insulated gate electrode disposed on a generally annular peripheral surface portion of said first well, said insulated gate electrode having a polycrystalline silicon layer with an inner periphery that is used for self-aligned formation of said first well, the improvement comprising:

• providing said polycrystalline silicon layer with a thickness that will mask ion implants of dopants;
• forming the second well by ion implanting a first dopant of said one conductivity type into an inner surface area of the first well exposed within said inner periphery of said polycrystalline silicon layer, the said ion implanting being done at a first energy at which said first dopant does not penetrate said polycrystalline silicon layer, whereby said second well is self-aligned with said inner periphery of said polycrystalline silicon layer, said second well having a bottom;
• completing formation of the second well by activating said first dopant without noticeably diffusing said first dopant vertically or horizontally, whereby said second well has an outer periphery that remains registered with said inner periphery of said polycrystalline silicon layer;
• forming a subsurface plate-like area of said opposite conductivity type having a higher dopant concentration than said first well in said first well below said bottom of said second well by ion implanting a second dopant of said opposite conductivity type into said inner surface area exposed within said inner periphery of said polycrystalline silicon layer, said ion implanting of said second dopant being done at a second energy which is higher than said first energy but at which said second dopant does not penetrate said polycrystalline silicon layer, whereby said plate-like area in said first well is self-aligned with said inner periphery of said polycrystalline silicon layer and said outer periphery of said second well;
• completing formation of the plate-like area by activating said second dopant without noticeably diffusing said second dopant vertically or horizontally, whereby said second well remains substantially registered with said inner periphery of said polycrystalline silicon layer and said outer periphery of said second well;
• etching through a central area of said second well into said plate-like area, effective to form a surface recess;
• implanting a third dopant of said opposite conductivity type into said surface recess at an energy at which said third dopant is targeted to lodge at said surface recess in said first well, and activating the third dopant without noticeably diffusing said third dopant of vertically or horizontally, effective to increase punch through voltage of said first well;
• and
• forming an electrode in said surface recess that is in electrical contact with each of said second well and said plate-like area in said first well.