US 5,843,625 A · Method of reducing via and contact dimensions beyond photolithography equipment limits

Abstract

A semiconductor process for forming an interlevel contact. A semiconductor wafer is provided with a semiconductor substrate, a first conductive layer formed on the substrate, and a dielectric layer formed on the conductive layer. A border layer, preferably comprising polysilicon or silicon nitride is formed on the dielectric layer. Portions of the border layer are then selectively removed to expose an upper surface of a spacer region of the dielectric layer, the selective removal of the border layer resulting in a border layer having an annular sidewall extending upward from the dielectric layer and encircling the spacer region. A spacer structure is then formed on the annular sidewall. Preferably, the spacer structure is formed by chemically vapor depositing a spacer material and anisotropically etching the spacer material to just clear in the planar regions with minimum overetch. The spacer structure thereby covers peripheral portions of the spacer region such that an upper surface of a contact region remains exposed. Portions of the dielectric layer within the contact region are then removed to form a via extending from an upper surface of the spacer structure to an upper surface of the first conductive layer. Preferably, the lateral dimension of the spacer region is approximately equal to the minimum feature size of a photolithography exposure apparatus in the lateral dimension of the via at substantially less than the minimum feature size of the photolithography exposure apparatus.

Claims15

Dependent claims

A semiconductor process for forming an interlevel contact, comprising:

providing a semiconductor wafer comprising a semiconductor substrate, a first conductive layer deposited on an upper surface of said semiconductor substrate, and an interlevel dielectric layer formed on an upper surface of said first conductive layer;
forming a border layer on said interlevel dielectric layer;
selectively removing portions of said border layer to expose an upper surface of a spacer region of said dielectric layer and such that said border layer includes an annular sidewall extending upwards from said upper surface of said dielectric layer and encircling said spacer region;
forming a spacer structure on said annular sidewall of said border layer, wherein said spacer structure covers peripheral portions of said spacer region of said dielectric layer such that an upper surface of a contact region of said dielectric layer remains exposed, and wherein said spacer structure comprises a material etch selective to said border layer;
and
removing portions of said dielectric layer within said contact region such that a via is formed extending from an upper surface of said dielectric layer to an upper surface of said first conductive layer.

3 more elements

A semiconductor process for forming a via comprising:

providing a semiconductor wafer, wherein said semiconductor wafer includes a semiconductor substrate, a first conductive layer formed on an upper surface of said semiconductor substrate, and an interlevel dielectric layer deposited on said first conductive layer;
forming a border layer on said interlevel dielectric layer;
depositing a photoresist layer on said border layer;
providing a photolithography exposure apparatus, wherein said photolithography exposure apparatus is capable of resolving a minimum feature dimension in said photoresist layer;
patterning said photoresist layer with said photolithography exposure apparatus to form a patterned photoresist layer such that a spacer region of said border layer is exposed, wherein a lateral dimension of said spacer region is approximately equal to said minimum feature dimension;
removing portions of said border layer within said spacer region to expose an upper surface of said dielectric layer within said spacer region and such that said border layer includes an annular sidewall extending from said upper surface of said dielectric layer at lateral boundaries of said spacer region:
forming a spacer structure on said annular sidewall of said border layer, wherein said spacer structure covers peripheral portions of said spacer region of said dielectric layer such that an upper surface of a contact region of said dielectric layer remains exposed, said contact region having a lateral dimension less than said minimum feature dimension, and wherein said spacer structure comprises a material etch selective to said border layer;
and
removing the portion of said dielectric layer within said contact region such that a via having a lateral dimension less than said minimum feature size and extending from an upper surface of said dielectric layer to an upper surface of said first conductive layer is formed.

6 more elements

Dependencies are inferred from the claim text.

Method of reducing via and contact dimensions beyond photolithography equipment limits

Life of this patent

Method of reducing via and contact dimensions beyond photolithography equipment limits

Life of this patent

Abstract

Claims15