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US 5,838,961 AGranted
Method of operation and apparatus for optimizing execution of short instruction branches
AssigneeCPU Technology, Inc.
InventorAlan G. Smith
Life of this patent
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AssigneeCPU Technology, Inc.
InventorAlan G. Smith
Estimating the term…
A technique for speeding CPU operations in handling branch instructions in which the target instructions is a short displacement away from its branch instruction is disclosed. When the target instruction is displaced within a predetermined number of instructions away, a logic block and counter issue an invalidating control signal which invalidates the execution of the branch instruction and instructions between the branch instruction and the target instruction. The invalidating control signal is removed when the target instruction is reached. Time is saved if the latency of the computer system is longer than the time required to cycle the instruction queue to the target instruction.
A method of operation in a CPU, said method comprising
A CPU in a computer system, said CPU executing a queue of instructions from a memory, said instruction queue including a branch instruction and its target instruction, said branch instruction having a value defining said displacement of said target instruction from said branch instruction, said CPU comprising
Dependencies are inferred from the claim text.