High-speed counter circuit

Abstract

A high-speed counter circuit comprising an input line for inputting a clock signal, at least two bit counters for generating a count value of at least two bits in response to the clock signal from the input line, at least one clock synchronizing circuit responsive to an output signal from at least one higher-order bit counter of the at least two bit counters, for transferring the clock signal from the input line to a lower-order bit counter of the at least two bit counters, and a delay circuit for delaying the clock signal from the input line by a propagation delay time of the at least one clock synchronizing circuit and applying the delayed clock signal to a highest-order bit counter of the at least two bit counters. According to the present invention, the high-speed counter circuit can minimize a delay time from the application of the clock signal to the generation of the count value to enhance the operation speed.

Dependencies are inferred from the claim text.