US 5,801,440 AGranted

Chip package board having utility rings

AssigneeACC Microelectronics Corporation

InventorsEdwin Chu, Hu-Kong Lai

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Abstract

A chip package includes a circuit board having a first surface with an inner die-attach region, an outer signal trace region and an intermediate utility region. Within the utility region are a number of traces for providing fixed electrical potentials to an integrated circuit die mounted within the die-attach region. In the preferred embodiment, the utility region includes a ring-like ground trace, a V.sub.DD trace and a segmented outer trace, with the segments of the segmented trace being connected to at least two fixed voltages for operating the integrated circuit die. Bond wires or leads of a leadframe include inner wire/lead ends connected to input/output pads of the die and include outer wire/lead ends connected to either a trace or trace segment in the utility region or a signal trace located in the outer signal trace region. The resulting chip package may be of the ball grid array type.

Claims22

Dependent claims

A substrate for an integrated circuit package comprising:

an insulative member having opposed first and second sides and having a semiconductor die-attach region on said first side;
a pattern of signal members arranged on said first side in spaced relationship to said die-attach region for electrical connection to a semiconductor die within said die-attach region by an array of conductive members;
a ground trace extending longitudinally on said first side in a utility region between said signal members and said die-attach region;
a power trace extending longitudinally on said first side in said utility region, said power trace being adjacent to said ground trace;
at least one around connection means for connecting to electrical ground, said around connection means disposed on said second side;
at least one power connection means for connecting to a power source, said power connection means disposed on said second side;
at least one ground via extending through said insulative member electrically coupling said around trace to said ground connection means;
and
at least one power via extending through said insulative member electrically coupling said power trace to said power connection means.

6 more elements

A chip package comprising:

a circuit board having opposed first and second surfaces, said first surface having an inner die-attach region and an outer signal trace region, said first surface further having a utility region surrounding said die-attach region to space said signal trace region from said die-attach region, said circuit board having an array of vias extending from said signal trace region to said second surface of said circuit board;
an integrated circuit die attached within said die-attach region of said first surface, said die having four edges and having a plurality of input/output pads;
a ground trace within said utility region at each of said four edges of said die, said ground trace being connected to means for connecting to electrical ground;
a first power trace within said utility region at each of said four edges of said die, said first power trace being connected to means for connecting to a fixed voltage source;
a plurality of second power traces connected to provide at least two different fixed voltages, said second power traces being within said utility region;
and
an array of conductors having inner wire/lead ends bonded to said input/output pads of said die and having outer wire/lead ends, said outer wire/lead ends including a first plurality connected to said ground trace and a second plurality connected to said power trace, said outer wire/lead ends further including a third plurality connected to sites within said signal trace region.

4 more elements

Dependencies are inferred from the claim text.