Graphics accelerator having minimal logic multiplexer system for sharing a microprocessor

A graphics accelerator comprising:

• a plurality of control units configured to generate a respective plurality of processor access signals, said control units configured to process graphics data via said processor access signals;
• a processor element having a control line, said processor element configured to execute said processor access signals to process said graphics data;
• a multiplexer control unit configured to generate a plurality of select signals;
• a plurality of logic gates equal in number to said plurality of control units with each logic gate having an input connected to a respective control unit, an output connected to said control line, and a select terminal connected to said multiplexer control unit for receiving a respective select signal;
• wherein said multiplexer control unit is configured to assert one of said select signals to said select terminal of one of said logic gates so as to enable said one logic gate and to permit one control unit, which is associated with said one logic gate, to gain control of said processor element by applying said one processor access signal from said one control unit to said control line;
• wherein said multiplexer control unit is configured to deassert said select signal to the select terminals of all other logic gates so as to disable all of the other logic gates and to prevent all other control units associated with the other logic gates from accessing said processor element, while said one control unit controls said processor element;
• wherein said multiplexer control unit is configured to produce start signals for selectively starting said control units and to produce stop signals for selectively stopping said control units;
• a second processor element having a second control line;
• a second plurality of logic gates equal in number to said plurality of control units with each logic gate in said second plurality having its input connected to its respective control unit, its output connected to said second control line, and its select terminal connected to said multiplexer control unit;
• and
• wherein said multiplexer control unit is configured to enable said one control unit to gain control of said second processor element by supplying another of said select signals to another logic gate in said second plurality which is associated with said one control unit,
• whereby said one control unit gains control of both said processor element and said second processor element when said one logic gate and said another logic gate receive said one select signal and said another select signal respectively from said multiplexer control unit.