Method for fabricating a multi-stage ROM

A method of forming a read only memory, comprising:

• successively forming a gate dielectric layer, a first polysilicon layer, a first dielectric layer, a second polysilicon layer and a second dielectric layer over a semiconductor substrate;
• patterning the second dielectric layer, the second polysilicon layer, the first dielectric layer, the first polysilicon layer and the gate dielectric layer at the same time, so that a region of an upper surface of the substrate is exposed, and a plurality of double-layer polysilicon lines remain;
• implanting impurities in the exposed region to form a plurality of source/drain regions which serve as bit lines;
• patterning the double-layer polysilicon lines to form a plurality of gates, wherein each of the gates combines with the adjacent source/drain regions to form memory cells including a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell;
• forming an insulating layer over the substrate and the memory cells;
• patterning the first memory cell and the second memory cell so that a portion of the first dielectric layer of the first memory cell and the second memory cell is exposed;
• and
• patterning the first memory cell so that a portion of the first polysilicon layer of the first memory cell is exposed, and patterning the third memory cell so that a portion of the second dielectric layer of the third memory cell is exposed.