Method for forming silicon-germanium/Si/silicon dioxide heterostructure using germanium implant
AssigneesSharp Microelectronics Technology, Inc., Sharp Kabushiki Kaisha
InventorTatsuo Nakato
Life of this patent
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Abstract
A method for fabricating a GeSi/Si/SiO.sub.2 heterostructure comprises the steps of: (a) providing a monocrystalline Si substrate; (b) defining a GeSi region within the Si substrate while leaving a Si cap overlying the GeSi region, the Si cap being an integral part of the monocrystalline substrate; and (c) oxidizing part of the Si cap to thereby produce the GeSi/Si/SiO.sub.2 heterostructure.
Claims34
A method for fabricating a combination of a conductive region having a relatively high charge carrier mobility and an insulator in a substrate composed of a first semiconductive material having a comparatively lower first charge carrier mobility, said method comprising the steps of:
- (a) implanting a mobility enhancing species into a first region of the low-mobility first semiconductive material to thereby convert the first region into a second region composed of a second semiconductive material having a second charge carrier mobility that is substantially higher than the first charge carrier mobility of the first semiconductive material;
- and thereafter
- (b) oxidizing a portion of the low-mobility first semiconductive material that is spaced apart from the second region to thereby create a heterostructure having three layers formed in the recited order of:
- (1) the second region into which the mobility enhancing species are implanted;
- (2) a third region which remains substantially composed of the low-mobility first semiconductive material;
- and (3) the oxidized portion of the low-mobility semiconductive material.
A method for fabricating a Ge.sub.x Si.sub.1-x /Si/SiO.sub.2 heterostructure comprising the steps of:
- providing a Si substrate;
- implanting Ge into the Si substrate to thereby define a Ge.sub.x Si.sub.1-x region within the Si substrate while leaving a Si cap overlying the Ge.sub.x Si.sub.1-x region, x being a value greater than zero but less than one;
- and
- oxidizing part of the Si cap to thereby produce said Ge.sub.x Si.sub.1-x /Si/SiO.sub.2 heterostructure.
A method for fabricating an integrated circuit including a Ge.sub.x Si.sub.1-x /Si/SiO.sub.2 heterostructure, said method comprising the steps of:
- providing a Si substrate having a top surface;
- implanting oxygen and/or nitrogen ions through the top surface of the substrate to form an isolation layer below and spaced away from the substrate top surface;
- annealing the substrate a first time to chemically combine the implanted oxygen and/or nitrogen with neighboring Si to thereby further form the isolation layer below the top surface of the substrate, wherein the formed isolation layer divides the Si substrate into a lower bulk portion and into an upper active portion, said active portion being disposed between the top surface of the substrate and the formed isolation layer;
- implanting Ge into a region of the active portion where the Ge-implanted region is spaced away from the top surface of the substrates
- annealing the substrate a second time to chemically combine the implanted Ge with neighboring Si to form Ge.sub.x Si.sub.1-x in the Ge-implanted region;
- selectively etching away areas of the active portion of the Si substrate essentially down to the isolation layer to thereby form one or more essentially isolated mesas, at least one of the formed mesas being for containing said Ge-implanted region;
- and
- oxidizing the Si surface area.
A method for fabricating an integrated circuit, said method comprising the steps of:
- (a) providing a monocrystalline Si substrate having a top surface;
- (b) implanting oxygen and/or nitrogen through the top surface of the substrate to form an isolation layer below and spaced away from the substrate top surface, said isolation layer dividing the Si substrate into a bulk lower portion and into an upper portion;
- (c) implanting Ge into one or more regions of the upper portion so as to form one or more the Ge-implanted regions that are spaced away from the top surface of the substrate, the spacing between the one or more Ge-implanted regions and the top surface defining capping Si;
- (d) annealing the substrate so as to further combine the implanted Ge with the Si in the one or more Ge-implanted regions;
- and
- (e) oxidizing a portion but not all of the capping Si.
A method for fabricating an integrated circuit, said method comprising the steps of:
- (a) providing a monocrystalline Si substrate having a top surface and a buried isolation layer formed below and spaced away from the substrate top surface, said isolation layer dividing the Si substrate into a lower portion and into an upper portion;
- (b) implanting Ge into one or more regions of the upper portion so as to form one or more the Ge-implanted regions that are spaced away from the top surface of the substrate, the spacing between the one or more Ge-implanted regions and the top surface defining capping Si;
- and
- (c) oxidizing a portion but not all of the capping Si.
Dependencies are inferred from the claim text.