FPGA redundancy

In an integrated circuit having an array of functional units and conducting line segments, each functional unit including a plurality of ports, said conducting line segments including line segments connected to said ports of said functional units and unconnected line segments, said line segments crossing each other in a predetermined pattern at intersections, said intersections having programmable devices connected to said crossing line segments programmable to connect said crossing line segments, said array being divided into a plurality of columns of individual functional units and surrounding programmable devices, wherein one or more of said columns are preselected to be redundant, a method of programming said integrated circuit to perform a desired function by programming selected ones of said programmable devices, said method comprising the steps of:

• testing said integrated circuit to obtain column defect information identifying a defective column;
• generating a first interconnection pattern of programmable devices to be programmed for said integrated circuit to perform said desired function, none of said programmable devices being included in said redundant columns;
• modifying said first interconnection pattern by displacing programmable devices to be programmed in said defective column by one column toward a redundant column and displacing columns between said defective column and said redundant column by one column toward said redundant column, thereby obtaining a second interconnection pattern of programmable devices to program for said integrated circuit to perform said desired function;
• and
• programming the programmable devices in said second interconnection pattern.