Process to manufacture a vertical gate-enhanced bipolar transistor

A process for manufacturing a gate-enhanced bipolar transistor, comprising the sequential steps of:

• providing a silicon body having an upper surface;
• by means of ion implantation, forming N+ and P+ buried layer regions, located a distance below said upper surface;
• depositing a layer of epitaxial silicon on said upper surface;
• by means of ion implantation followed by thermal drive-in, forming N-type collector sink and P-well regions that extend from said upper surface to said buried layer regions;
• growing a first layer of silicon oxide on said upper surface;
• depositing a first layer of silicon nitride on the first layer of silicon oxide;
• depositing a second layer of silicon oxide on said first layer of silicon nitride;
• anisotropically etching a trench, having the shape of a hollow square, located within said P-well region and having an inside surface, to a depth such that the trench extends through the second layer of silicon oxide, the first layer of silicon nitride, the first layer of silicon oxide, and the P-well region, and partially through the N+ buried layer;
• growing a third layer of silicon oxide on the trench's inside surface;
• filling the trench with N+ polysilicon, thereby forming a gate electrode;
• growing a fourth layer of silicon oxide on the N+ polysilicon, said fourth oxide layer being thicker than said second oxide layer;
• removing the second layer of silicon oxide and the first layer of silicon nitride, thereby exposing the first layer of silicon oxide;
• depositing a second layer of silicon nitride on the first and fourth layers of silicon oxide;
• selectively etching the second layer of silicon nitride;
• increasing the thickness of said first and fourth layers of silicon oxide, wherever they are not covered by silicon nitride, thereby forming regions of field oxide;
• removing said second layer of silicon nitride and the oxide layer that is immediately beneath it, thereby exposing said upper surface wherever it is not covered by field oxide;
• depositing a first layer of undoped polysilicon;
• implanting arsenic ions, said ions having a range of energies such that the layer of undoped polysilicon is transformed into a layer of N-type polysilicon;
• depositing a fifth silicon oxide layer on said layer of N-type polysilicon;
• depositing a third layer of silicon nitride on said fifth silicon oxide layer;
• patterning and etching the fifth silicon oxide layer and the third silicon nitride layer in an area located inside the hollow square, thereby forming a base window opening mask;
• growing a sixth silicon oxide layer on both sides of the N-type polysilicon layer and the exposed upper surface;
• depositing a fourth layer of silicon nitride;
• depositing a second polysilicon layer;
• anisotropically etching said layers of polysilicon and silicon nitride until the sixth silicon oxide layer is exposed, thereby forming self-aligned spacers;
• lightly etching exposed portions of the sixth silicon oxide layer, thereby forming a fully opened base window;
• depositing a third layer of polysilicon;
• implanting boron ions, said ions having a range of energies such that said third layer of polysilicon is converted to P type;
• patterning and etching the third layer of polysilicon so as to define circuit connections and then heating it so that boron ions are driven into the silicon at the base window opening, thereby forming a P+ base contact;
• depositing a layer of low temperature oxide over all exposed surfaces;
• heating the silicon body to a sufficient extent as to cause the low temperature oxide layer to flow, thereby providing for improved planarity;
• etching contact holes through said layer of low temperature oxide, said fourth layer of silicon nitride, and said fifth layer of silicon oxide;
• and
• depositing and then selectively etching a metal layer to form wiring that contacts the gate, the base window opening, the emitter, and the N-type collector sink.