Periodic waveform generating circuit
AssigneeNippon Telegraph and Telephone Corporation
InventorsKunihiro Arai, Hideaki Matsuzaki
Life of this patent
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AssigneeNippon Telegraph and Telephone Corporation
InventorsKunihiro Arai, Hideaki Matsuzaki
Estimating the term…
A first partial circuit is formed by grounding the emitter electrode of a first negative differential resistive element, connecting the emitter electrode of a second negative differential resistive element to the collector electrode of the first negative differential resistive element, and connecting a first field-effect transistor in parallel with the first negative differential resistive element. A second partial circuit is formed by grounding the emitter electrode of a third negative differential resistive element, connecting the emitter electrode of a fourth negative differential resistive element to the collector electrode of the third negative differential resistive element, and connecting a second field-effect transistor in parallel with the third negative differential resistive element. An output from the first partial circuit is input to the input of the second partial circuit. The inversion of the output of the second partial circuit is input to the input of the first partial circuit. A clock signal and a signal whose phase is opposite to that of the clock signal are applied to the collector electrodes of the second and fourth negative differential resistive elements, respectively. A frequency-divided signal of the clock signal is output from each partial circuit.
A periodic waveform generating circuit comprising:
A periodic waveform generating circuit comprising:
A periodic waveform generating circuit comprising a plurality of groups each comprising not less than two cascaded units each comprising
Dependencies are inferred from the claim text.