Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping

A programmable read only memory (PROM) device, comprising:

• semiconducting substrate of a first conductivity type;
• a source, said source comprising a region of said semiconducting substrate doped to have a conductivity opposite that of said semiconducting substrate;
• a drain, spaced from said source, said drain comprising a region of said semiconducting substrate doped to have a conductivity opposite that of said semiconducting substrate, a channel being formed between said source and said drain within said semiconducting substrate;
• a first insulating layer overlaying and covering said channel portion of said semiconducting substrate;
• a nonconducting charge trapping layer formed on and overlaying said first insulating layer;
• a second insulating layer formed on and overlaying said nonconducting charge trapping layer;
• a gate, said gate comprising an electrically conductive material formed on and overlaying said second insulating layer;
• wherein said cell is adapted to receive and retain electrons injected into said nonconducting charge trapping layer in a region close to said source forming a bit;
• and
• wherein said memory is adapted to be read in a direction opposite to that in which it was programmed, such that a lower limit for the voltage applied to said gate during reading said bit is the voltage at which sufficient inversion is generated in said channel whereby an unprogrammed state can be sensed, an upper limit for the voltage applied to said gate during reading said bit is the voltage at which the voltage across a region of said channel beneath the trapped charge in said charge storage region is below the voltage applied to said source during reading said bit.

A method of programming and reading a programmable read only memory (PROM) cell, said PROM cell having a semiconducting substrate, source, drain with a channel therebetween and a gate above said channel separated therefrom by a nonconducting charge trapping material sandwiched between first and second silicon dioxide layers, said method comprising the steps of:

• programming in a forward direction by injecting electrical charge into said charge trapping material utilizing hot electron injection for a sufficient time that electrical charge becomes trapped asymmetrically in a charge trapping region of said charge trapping material close to said drain forming a bit, said electric charge being injected until the threshold voltage of said memory gate reaches a predetermined level when said memory cell is read in the reverse direction from which it was programmed;
• said asymmetrical charge injection for said bit being generated by applying programming voltages to said drain and said gate and grounding said source;
• and
• reading in reverse direction by applying read voltages to said source and said gate and grounding said drain, and subsequently sensing whether or not current flows through said memory cell from said source to said drain.

A programmable read only memory (PROM) cell, comprising:

• a semiconductor substrate of a first conductivity type containing therein a source region and a drain region each of a second conductivity type opposite to said first conductivity type and separated from each other by a channel region normally of said first conductivity type;
• a dielectric formed over said channel region, said dielectric being capable of holding selected charge in a portion thereof above and adjacent to said drain region, said dielectric including a first layer of silicon oxide, a second layer of silicon oxide and a charge trapping material formed between said first layer of silicon oxide and said second layer of silicon oxide;
• a gate comprising an electrically conductive layer formed on and overlaying said dielectric;
• a first voltage source capable of being connected to said drain, a second voltage source capable of being connected to said gate and a third voltage source capable of being connected to said source;
• and
• a control both for causing said first voltage source to apply a first voltage to said drain, said second voltage source to apply a second voltage to said gate, and said third voltage source to apply a third voltage to said source, thereby to cause electrons to be injected by hot electron injection into said portion of said dielectric and for causing said first voltage source to apply a fourth voltage to said drain, said second voltage source to apply a fifth voltage to said gate and said third voltage source to apply a sixth voltage to said source thereby to cause said memory cell to read in the reverse direction from the direction in which the cell was programmed.

A semiconductor memory cell, comprising:

• a substrate of a first conductivity type including a source region of a second conductivity type opposite the said first conductivity type and a drain region of said second conductivity type, said source and drain being respectively spaced from each other by a channel region normally of said first conductivity type formed therebetween;
• dielectric capable of holding an electrical charge in a charge trapping region thereof formed over said channel region;
• a conductive gate formed over said dielectric;
• means for applying a first voltage to said source region and a second voltage to said gate region thereby to cause electrons to be lodged on and stored in said charge trapping region associated with the said dielectric;
• and
• means for applying a third voltage to said source and a fourth voltage to said gate thereby to cause a current to be read indicating the presence or absence of a stored charge in said dielectric, the fourth voltage being between a fifth voltage sufficient to invert said channel with no charge in said charge trapping region and a sixth voltage sufficient to create a voltage beneath said third voltage at a point in said channel beneath an edge of said charge trapping region with charge stored therein.

A programmable read only memory (PROM) cell, comprising:

• a semiconductor substrate of a first conductivity type;
• a source comprising a region of said semiconducting substrate doped to have a conductivity opposite that of said semiconducting substrate;
• a drain spaced from said source, comprising a region of said semiconducting substrate doped to have a conductivity opposite that of said semiconducting substrate;
• a channel formed in the space between said source and said drain within said semiconducting substrate;
• a first insulating layer overlaying and covering said channel;
• a non conducting charge trapping layer formed on and overlaying said first insulating layer;
• a second insulating layer formed on and overlaying said non conducting charge trapping layer;
• a gate comprising an electrically conductive material formed on and overlaying said second insulating layer;
• and
• wherein said charge trapping layer is formed so as to receive and retain a first selected amount of charge in a region of said non-conducting, charge-trapping layer close to and above said drain, said charge-trapping layer comprising a layer of silicon nitride having a thickness selected to ensure that the lateral electric field associated with the trapped charge is below the lateral electric field which would cause significant lateral diffusion of the stored charge and said first selected amount of charge is sufficient to cause a desired increase in the threshold voltage required to invert said channel when said cell is read in the reverse direction but is not sufficient to cause the same desired increase in the threshold voltage required to invert the channel when the cell is read in the forward direction.