Apparatus and methods for generating cell layouts

A computer-implemented apparatus for generating a cell layout representative of a CMOS logic cell, comprising:

• a pMOS transistor layout generator, said pMOS transistor layout generator generates a first set of layout data representative of a plurality of substantially similar pMOS relatively low strength transistor groups, transistors in said plurality of substantially similar pMOS relatively low strength transistor groups being oriented along a first direction;
• an nMOS transistor layout generator, said nMOS transistor layout generator generates a second set of layout data representative of a plurality of substantially similar nMOS relatively low strength transistor groups, transistors in said plurality of nMOS relatively low strength transistor groups being oriented along said first direction;
• a polysilicon conductor generator, said polysilicon conductor generator generates a third set of layout data representative of a plurality of polysilicon conductors for coupling transistors in said plurality of substantially similar pMOS relatively low strength transistor groups with complementary ones of transistors in said plurality of substantially similar nMOS relatively low strength transistor groups, thereby creating a plurality of low strength gates;
• a metal one conductor generator, said metal one conductor generator generates a fourth set of layout data representative of a first metal one conductor, said first metal one conductor being coupled to said plurality of polysilicon conductors to create a relatively higher strength gate out of said plurality of low strength gates;
• and
• a well ties generator for generating a fifth set of layout data representative of a set of well ties, said set of well ties being positioned, responsive to a user input, at one of a first location and a second location, said first location being disposed directly above a well of said CMOS logic cell and aligned with both said first half dual structure and said second half dual structure along said first direction, said second location being disposed beside one of said plurality of substantially similar pMOS relatively low strength transistor groups and said plurality of substantially similar nMOS relatively low strength transistor groups.

A computer-implemented apparatus for generating a cell layout representative of a CMOS logic cell, comprising:

• a pMOS transistor layout generator, said pMOS transistor layout generator generates a first set of layout data representative of a plurality of substantially similar pMOS relatively low strength transistor groups, transistors in said plurality of substantially similar pMOS relatively low strength transistor groups being oriented along a first direction;
• an nMOS transistor layout generator, said nMOS transistor layout generator generates a second set of layout data representative of a plurality of substantially similar nMOS relatively low strength transistor groups, transistors in said plurality of nMOS relatively low strength transistor groups being oriented along said first direction;
• a polysilicon conductor generator, said polysilicon conductor generator generates a third set of layout data representative of a plurality of polysilicon conductors for coupling transistors in said plurality of substantially similar pMOS relatively low strength transistor groups with complementary ones of transistors in said plurality of substantially similar nMOS relatively low strength transistor groups, thereby creating a plurality of low strength gates;
• a metal one conductor generator, said metal one conductor generator generates a fourth set of layout data representative of a first metal one conductor, said first metal one conductor being coupled to said plurality of polysilicon conductors to create a relatively higher strength gate out of said plurality of low strength gates;
• and
• a well ties generator for dynamically generating a fifth set of layout data representative of a set of well ties, said set of well ties being positioned dynamically, responsive to an inputted set of predefined conditions, at one of a first location and a second location, said first location being disposed directly above a well of said CMOS logic cell and aligned with both said first half dual structure and said second half dual structure alone said first direction, said second location being disposed beside one of said plurality of substantially similar pMOS relatively low strength transistor groups and said plurality of substantially similar nMOS relatively low strength transistor groups.

A computer readable media containing program instructions for creating a cell layout representative of a CMOS logic cell in a digital computer, comprising:

• a first set of program instructions for creating a first half dual structure in a first memory of said digital computer, said first half dual structure comprising a first transistor group and a second transistor group, said second transistor group being substantially identical to said first transistor group, transistors in said first transistor group and said second transistor group being of a first type and oriented along a first direction;
• a second set of program instructions for creating a second half dual structure in a second memory of said digital computer, said second half dual structure comprising a third transistor group and a fourth transistor group, said fourth transistor group being substantially identical to said third transistor group, transistors in said third transistor group and said fourth transistor group being of a second type complementary to said first type and oriented along said first direction;
• a third set of program instructions for coupling, using a processor in said digital computer, a polysilicon conductor to an input of a first complementary transistor group, said first complementary transistor group comprising a selected transistor in said first transistor group and a selected transistor in said third transistor group, said input of said first complementary transistor group being coupled to gates of said selected transistor in said first transistor group and said selected transistor in said third transistor group;
• a fourth set of program instructions for coupling, using said processor in said digital computer, a polysilicon conductor to an input of a second complementary transistor group, said second complementary transistor group comprising a selected transistor in said second transistor group and a selected transistor in said fourth transistor group, said input of said second complementary transistor group being coupled to gates of said selected transistor in said second transistor group and said selected transistor in said fourth transistor group;
• a fifth set of program instructions for coupling, using said processor in said digital computer, a first metal one conductor to said first polysilicon conductor and said second polysilicon conductor, thereby creating a logic gate;
• and
• a sixth set of program instructions for dynamically placing, responsive to an input parameter, a set of well ties at one of a first location and a second location, said first location being disposed directly above a well of said CMOS logic cell and aligned with both said first half dual structure and said second half dual structure alone said first direction, said second location being disposed beside one of said first and second half dual structures.