Dynamic latching device

A flip-flop comprising:

• a first dynamic pull-up element coupled to precharge a first output node to a precharged state;
• a first transistor coupled to discharge the first output node and having a control electrode coupled to a data input providing data for storage in the flip-flop;
• a pull-down device coupled to enable a path for the first transistor to discharge the first output node;
• and
• a delay block coupled to provide a delayed clock signal from a clock signal, whereby the pull-down device enables the first transistor to discharge the first output node during a delay period after a transition of the clock signal and before a resulting transition in the delayed clock signal.

A method of performing a flip-flop logic function comprising the steps of:

• generating a delayed clock signal from a clock signal, wherein a transition of the delayed clock signal follows a corresponding transition of the clock signal after a delay period;
• precharging a first node to a first level before the transition in the clock signal;
• providing data at a data input for storage in the flip-flop at least a minimum setup time before the transition in the clock signal;
• permitting the data input to change a level at the first node during the delay period;
• and
• outputting the level at the first node as an output of the flip-flop.