Dynamic bus reconfiguration logic

A multi-processor computer, comprising:

• a plurality of processors;
• a plurality of memories;
• a plurality of pathway control units, each pathway control unit controlling read and write access to one memory of the plurality of memories;
• a resource allocator, coupled to the pathway control units and the plurality of processors, for allocating access to the pathway control units as requested by processors, the resource allocator operating on control signals provided for a current access clock cycle and comprising:
• a first circuit for determining a pathway data width requested by each processor making an access request for a current access clock cycle, wherein each processor specifies a particular pathway data width using address lines from the processor;
• a second circuit for prioritizing processor requests for the current access clock cycle, including logic for allowing multiple accesses in the current access clock cycle where more than one processor requests less than all of an available pathway data width provided by the plurality of memories;
• a third circuit for coupling a processor granted an access request to a memory requested by the processor, wherein coupling for each access clock cycle is independent of coupling for prior access clock cycles.

A method for memory access of a plurality of memories by a plurality of processors, comprising the steps of:

• allocating a unique processor address space to each possible pathway data width;
• issuing a request from a processor for a memory access, the request including an indication of a requested pathway data width and address, thereby indicating a requested pathway data width by a subset of address lines;
• prioritizing requests from processors for memory access to determine a request to be granted in an access clock cycle;
• if multiple processors request an access for the access clock cycle and the requested pathway data widths and addresses are such that they do not overlap, granting multiple requests to multiple processors for the access clock cycle;
• coupling processors with memories as indicated by the granted access requests in the access clock cycle.