PMOS single-poly non-volatile memory structure

A P-channel non-volatile memory cell, comprising:

• a P+ source and a P+ drain formed in an N-well;
• a channel extending between said source and said drain;
• a floating gate overlying said channel;
• a first diffusion region formed in said N-well and underlying a first portion of said floating gate, said first diffusion region serving as a control gate of said cell;
• and
• a second diffusion region formed in said N-well and underlying a second portion of said floating gate, said second diffusion region serving as an erase gate of said cell, wherein said memory cell is erased by applying approximately -6.5 volts to said control gate, applying approximately 8 volts to said erase gate, grounding said N-well, and coupling said source and said drain to a floating potential.

A P-channel non-volatile memory cell, comprising:

• a P+ source and a P+ drain formed in an N-well;
• a channel extending between said source and said drain;
• a floating gate overlying said channel;
• a first diffusion region formed in said N-well and underlying a first portion of said floating gate, said first diffusion region serving as a control gate of said cell;
• a second diffusion region formed in said N-well and underlying a second portion of said floating gate, said second diffusion region serving as an erase gate of said cell;
• and
• a third diffusion region formed in said N-well, said third diffusion region being of a conductivity type opposite that of said erase gate, wherein said erase gate is formed within said third diffusion region whereby said third diffusion region electrically isolates said erase gate from said N-well.

A P-channel non-volatile memory cell, comprising:

• a P+ source and a P+ drain formed in an N-well;
• a channel extending between said source and said drain;
• a floating gate overlying said channel;
• a first diffusion region formed in said N-well and underlying a first portion of said floating gate, said first diffusion region serving as a control gate of said cell;
• a second diffusion region formed in said N-well and underlying a second portion of said floating gate, said second diffusion region serving as an erase gate of said cell;
• and
• a third diffusion region formed in said N-well, said third diffusion region being of a conductivity type opposite that of said control gate, wherein said control gate is formed within said third diffusion region whereby said third diffusion region electrically isolates said control gate from said N-well.

A P-channel non-volatile memory cell, comprising:

• a P+ source and a P+ drain formed in an N-well;
• a channel extending between said source and said drain;
• a floating gate overlying said channel;
• a first diffusion region formed in said N-well and underlying a first portion of said floating gate, said first diffusion region serving as a control gate of said cell;
• and
• a second diffusion region formed in said N-well and underlying a second portion of said floating gate, said second diffusion region serving as an erase gate of said cell, wherein said memory cell is read by applying approximately 0.7 volts to said drain and applying approximately 3 volts to said source, said control gate, and said N-well.