Gray code counter
AssigneeVLSI Technology, Inc.
InventorNeal Wingen
Life of this patent
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AssigneeVLSI Technology, Inc.
InventorNeal Wingen
Estimating the term…
A Gray Code counter includes first translator logic, binary incrementing/decrementing logic, second translator logic, and a clocked storage device. The first translator logic receives at an input a Gray Code number, I.sub.gray n:0! which the first translator translates into a binary number, I.sub.bin n:0!. The binary incrementing/decrementing logic either increments or decrements the binary number I.sub.bin n:0! to produce an incremented/decremented binary number, Z.sub.bin n:0!. The second translator logic translates the incremented/decremented binary number Z.sub.bin n:0! into an incremented/decremented Gray Code number, Z.sub.gray n:0!. The clocked storage device stores the incremented/decremented Gray Code number, Z.sub.gray n:0!. The clocked storage device also feeds the incremented/decremented Gray Code number, Z.sub.gray n:0!, to the input of the first translator logic.
An incrementer which increments a Gray Code number I.sub.gray n:0! to produce an incremented Gray Code number Z.sub.gray n:0!, the incrementer comprising:
A decrementer which decrements a Gray Code number I.sub.gray n:0! to produce a decremented Gray Code number Z.sub.gray n:0!, the decrementer comprising:
A Gray Code counter comprising:
A Gray Code counter comprising:
A method by which a Gray Code counter is implemented, the method comprising the following steps:
A method by which a Gray Code counter is implemented, the method comprising the following steps:
Dependencies are inferred from the claim text.