Polysilicon pillar diode for use in a non-volatile memory cell

A memory matrix comprising:

• a plurality of first address lines;
• a plurality of second address lines;
• a plurality of diodes being formed by depositing at least three silicon layers on a substrate and by selectively etching through said silicon layers to form a plurality of pillars of silicon layers, wherein each of said pillars forms a diode, wherein said silicon layers comprise an N- layer an N+ layer, and a P+ layer, and wherein each of said plurality of pillars has a first end and a second end, the first end of each of said plurality of pillars being coupled to a respective one of said plurality of first address lines;
• and
• a plurality of memory elements, each of said plurality of memory elements having a first electrode coupled to said second end of a respective one of said plurality of pillars, a second electrode coupled to a respective one of said plurality of second address lines, and a layer of programmable resistive material coupled between said first electrode and said second electrode.

A memory matrix comprising:

• a plurality of first address lines;
• a plurality of second address lines;
• a plurality of diodes, each of said plurality of diodes being formed by a pillar comprised of at least three silicon layers, wherein said silicon layers comprise an N- layer, an N+ layer, and a P+ layer;
• and
• a plurality of memory elements, each of said plurality of memory elements having a layer of resistive material being electrically coupled to a respective one of said plurality of diodes.

A memory matrix comprising:

• a plurality of first address lines being disposed in a plurality of trenches recessed in a dielectric base, said plurality of trenches being coated with a layer of TiN;
• a plurality of second address lines;
• a plurality of diodes being formed by depositing at least three silicon layers on a substrate and by selectively etching through said silicon layers to form a plurality of pillars of silicon layers, wherein each of said pillars forms a diode, and wherein each of said plurality of pillars has a first end and a second end, the first end of each of said plurality of pillars being coupled to a respective one of said plurality of first address lines;
• and
• a plurality of memory elements, each of said plurality of memory elements having a first electrode coupled to said second end of a respective one of said plurality of pillars, a second electrode coupled to a respective one of said plurality of second address lines, and a layer of programmable resistive material coupled between said first electrode and said second electrode.

A memory matrix comprising:

• a plurality of first address lines;
• a plurality of second address lines;
• a plurality of diodes being formed by depositing on a substrate a plurality of silicon layers and a layer of TiN and by selectively etching through said plurality of silicon layers to form a plurality of pillars of silicon layers, wherein each of said plurality of pillars forms a diode, and wherein each of said plurality of pillars has a first end and a second end, the first end of each of said plurality of pillars being coupled to a respective one of said plurality of first address lines;
• and
• a plurality of memory elements, each of said plurality of memory elements having a first electrode coupled to said second end of a respective one of said plurality of pillars, a second electrode coupled to a respective one of said plurality of second address lines, and a layer of resistive material coupled to said first electrode and to said second electrode.