Programmable array interconnect latch

An integrated circuit having a plurality of programmable logic cells, a programmable interconnect network for connecting the programmable logic cells, and at least one programmable interface circuit connected within said programmable interconnect network, said programmable interface circuit comprising:

• an input node and an output node;
• circuit, connected between said input and output nodes, for selectively providing a buffered output signal to said output node, said buffered output signal being related to a logic state at said input node;
• and
• a signal storage circuit connected to said input node for selectively storing a logic state received from said input node,
• wherein said programmable interface circuit further comprises a secondary input node and a secondary output node;
• and
• said signal storage circuit further comprises:
• primary selective latch selectively coupled to said input node or said secondary input node for selectively storing a logic state received from either said input node or said secondary input node;
• and
• secondary selective latch selectively coupled to said primary selective latch and coupled to said secondary output node for providing latched data to said secondary output node, said latched data being representative of a previously stored logic state of said primary selective latch.

An integrated circuit having a plurality of programmable logic cells, a programmable interconnect network for connecting the programmable logic cells, and at least one programmable interface circuit connected within said programmable interconnect network, said programmable interface circuit comprising:

• an input node and an output node;
• a circuit, connected between said input and output nodes, for selectively providing a buffered output signal to said output node, said buffered output signal being related to a logic state at said input node;
• and
• a signal storage circuit connected to said input node for selectively storing a logic state received from said input node,
• wherein said integrated circuit further comprises a plurality of operational control signal paths and a plurality of test control signal paths, said integrated circuit further comprising:
• programmable coupler selectively connecting at least one signal path of the group consisting of at least one select operational control signal path of said plurality of operational control signal paths and at least one select test control signal path of said plurality of test control signal paths to said signal storage circuit such that said signal storage circuit can be selectively employed during testing of said integrated circuit or during operation of said integrated circuit.

An integrated circuit having a plurality of programmable logic cells, a programmable interconnect network for connecting the programmable logic cells, and at least one programmable interface circuit connected within said programmable interconnect network, said programmable interface circuit comprising:

• an input node and an output node;
• a circuit, connected between said input and output nodes, for selectively providing a buffered output signal to said output node, said buffered output signal being related to a logic state at said input node;
• and
• a signal storage circuit connected to said input node for selectively storing a logic state received from said input node,
• wherein said signal storage circuit comprises:
• a secondary input node for receiving serial input data;
• a secondary output node for sending out serial output data;
• primary and secondary latches retaining respective primary and secondary latched data;
• a first selective coupler disposed between said input node and said primary latch, said first selective coupler selectively coupling primary data of said input node to said primary latch in accordance with a first clock signal so as to capture the primary data as said primary latched data;
• a second selective coupler disposed between said secondary input node and said primary latch, said second selective coupler selectively coupling serial input data of said secondary input node to said primary latch in accordance with a second clock signal so as to capture the serial input data as said primary latched data;
• and
• a third selective coupler disposed between said primary latch and said secondary latch, said third selective coupler selectively coupling said primary latch to said secondary latch in accordance with a third clock signal so as to update the secondary latched data of said secondary latch in accordance with said primary latched data, data representative of the secondary latched data being provided at said secondary output node as serial output data.

A method of operating an integrated circuit, comprising the steps of:

• providing an integrated circuit having a plurality of programmable logic cells, a programmable interconnect network for connecting the programmable logic cells, a programmable buffer for selectively buffering a signal within a given programmable interconnect of the programmable interconnect network, and a signal storage circuit of a first serial scan chain for selectively capturing and storing data of, and providing data to, said given programmable interconnect;
• configuring, as a configured logic circuit, select programmable logic cells of said plurality of logic cells and select programmable interconnects of said programmable interconnect network and including said given programmable interconnect, for implementing a desired logic design;
• applying data to said configured logic circuit for stimulation thereof;
• selectively operating said signal storage circuit for capturing data of said given programmable interconnect, as effected by processing of said configured logic circuit in response to stimulation by said data, into said signal storage circuit of said first scan chain;
• and
• scanning said captured data out of said first scan chain.

A method of operating an integrated circuit, comprising the steps of:

• providing an integrated circuit having a plurality of programmable logic cells, a programmable interconnect network for connecting the programmable logic cells, a programmable buffer for selectively buffering a signal within a given programmable interconnect of the programmable interconnect network, and a signal storage circuit of a serial scan chain for selectively capturing and storing data from, and providing data to, said given programmable interconnect;
• configuring, as a configured logic circuit, select programmable logic cells of said plurality of logic cells and select programmable interconnects of said programmable interconnect network and including said given programmable interconnect, for implementing a desired logic design;
• scanning data serially into said signal storage circuit via said serial scan chain;
• and
• selectively operating said signal storage circuit for presenting said data to said given programmable interconnect as input data to the configured logic circuit.

A method of operating an integrated circuit, comprising the steps of:

• providing an integrated circuit having a plurality of programmable logic circuits, a programmable interconnect network for connecting the programmable logic circuits, programmable buffers for selectively buffering associated signals within respective interconnects of the programmable interconnect network, and a plurality of signal storage circuits in parallel with respective programmable buffers for selectively capturing and storing data of associated said programmable interconnects or selectively outputting stored data thereof onto associated said programmable interconnects;
• configuring, as a configured logic circuit, select programmable logic circuits of said plurality of logic circuits and select programmable interconnects of the programmable interconnect network, for implementing a desired logic design;
• configuring first select signal storage circuits of said plurality of signal storage circuits as an input serial scan chain across at least one input line of said configured logic circuit;
• configuring second select signal storage circuits of said plurality of signal storage circuits as an output serial scan chain across at least one output line of said configured logic circuit;
• scanning data into said input serial scan chain;
• selectively disabling the programmable buffer(s) of the select programmable interconnects as associated with said at least one input line of said configured logic circuit;
• selectively enabling said first select signal storage circuit of said input serial scan chain to apply the data to said configured logic circuit;
• processing the data by the configured logic circuit;
• selectively operating said second select signal storage circuits of said output serial scan chain for capturing configured logic circuit output data at said at least one output line;
• and
• selectively operating said second select signal storage circuits of said output serial scan chain for scanning said captured data out of said output serial scan chain.

A programmable gate array, PGA, having a plurality of programmable logic circuits and a plurality of programmable interconnects, wherein at least one programmable interconnect of said plurality of programmable interconnects includes a programmable interface circuit disposed therein, said programmable interface circuit comprising:

• a first node coupled to a first portion of said at least one programmable interconnect;
• a second node coupled to a second portion said at least one programmable interconnect;
• a programmable coupling circuit disposed between said first and second nodes for selectively propagating a signal therebetween in accordance with a first select signal;
• and
• an LSSD register disposed between said first and second nodes, said LSSD register having:
• a primary input coupled to said first node for receiving primary data;
• a serial input for receiving serial data;
• first selective latch selectively coupled to said primary input or said serial input for selectively capturing, as captured data, either primary data of said primary input as effected by a pulse of a C-clock, or serial data of said serial input as effected by a pulse of an A-clock;
• second selective latch selectively coupled to said first selective latch for latching data therein, as latched data, corresponding to said captured data of said first selective latch, the latching of said latched data being effected by a pulse of a B-clock;
• a serial output for sending out serial output data corresponding to said latched data of said second selective latch;
• and
• a programmable primary output for selectively outputting to said second node primary output data corresponding to said latched data, the primary output data being selectively applied to said second node in accordance with a second select signal.